Simulation Results: edn

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.30 %
  • code
  • 95.63 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.260s 18.567us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.840s 64.035us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.850s 15.904us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 2.350s 1585.654us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.240s 40.628us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.420s 99.716us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.850s 15.904us 20 20 100.00
edn_csr_aliasing 1.240s 40.628us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 44.770s 2280.216us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 44.770s 2280.216us 300 300 100.00
genbits 300 300 100.00
edn_genbits 44.770s 2280.216us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.540s 22.076us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.360s 32.240us 200 200 100.00
errs 100 100 100.00
edn_err 1.300s 22.028us 100 100 100.00
disable 100 100 100.00
edn_disable 1.110s 21.240us 50 50 100.00
edn_disable_auto_req_mode 1.610s 36.720us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 5.390s 422.593us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.900s 25.344us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.680s 358.588us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.970s 135.960us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.970s 135.960us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.840s 64.035us 5 5 100.00
edn_csr_rw 0.850s 15.904us 20 20 100.00
edn_csr_aliasing 1.240s 40.628us 5 5 100.00
edn_same_csr_outstanding 1.150s 148.806us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.840s 64.035us 5 5 100.00
edn_csr_rw 0.850s 15.904us 20 20 100.00
edn_csr_aliasing 1.240s 40.628us 5 5 100.00
edn_same_csr_outstanding 1.150s 148.806us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.670s 444.212us 20 20 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.890s 20.764us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.360s 32.240us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.360s 32.240us 200 200 100.00
edn_sec_cm 6.750s 605.955us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.360s 32.240us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.670s 444.212us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
edn_stress_all_with_rand_reset 112.510s 21755.463us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1142) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 31955292887911654554213458257496735147485559113002526817313845762306674563013 184
UVM_ERROR @ 1344719119 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1344719119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---