Simulation Results: edn

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.32 %
  • code
  • 96.39 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.030s 17.865us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.130s 16.040us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.060s 55.107us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.190s 256.581us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.080s 27.339us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.710s 74.588us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.060s 55.107us 20 20 100.00
edn_csr_aliasing 1.080s 27.339us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 3.780s 518.919us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 3.780s 518.919us 300 300 100.00
genbits 300 300 100.00
edn_genbits 3.780s 518.919us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.010s 24.770us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.340s 31.941us 200 200 100.00
errs 100 100 100.00
edn_err 1.140s 23.361us 100 100 100.00
disable 100 100 100.00
edn_disable 0.940s 21.770us 50 50 100.00
edn_disable_auto_req_mode 1.140s 36.550us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.100s 430.959us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.140s 18.214us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.530s 108.589us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.260s 784.964us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.260s 784.964us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.130s 16.040us 5 5 100.00
edn_csr_rw 1.060s 55.107us 20 20 100.00
edn_csr_aliasing 1.080s 27.339us 5 5 100.00
edn_same_csr_outstanding 1.230s 147.156us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.130s 16.040us 5 5 100.00
edn_csr_rw 1.060s 55.107us 20 20 100.00
edn_csr_aliasing 1.080s 27.339us 5 5 100.00
edn_same_csr_outstanding 1.230s 147.156us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.040s 373.213us 20 20 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.860s 18.297us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.340s 31.941us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.340s 31.941us 200 200 100.00
edn_sec_cm 4.230s 2088.305us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.340s 31.941us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.040s 373.213us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 84.390s 7732.343us 50 50 100.00

Error Messages

   Test seed line log context