Simulation Results: hmac

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.98 %
  • code
  • 99.33 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.420s 2400.315us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.200s 20.890us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.260s 45.937us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 13.980s 1565.157us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 8.830s 836.936us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 308.080s 149852.031us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.260s 45.937us 20 20 100.00
hmac_csr_aliasing 8.830s 836.936us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 77.550s 23013.040us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 77.720s 14699.464us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 264.270s 28989.002us 30 30 100.00
hmac_test_sha384_vectors 529.920s 57178.928us 75 75 100.00
hmac_test_sha512_vectors 518.700s 51727.670us 75 75 100.00
hmac_test_hmac256_vectors 15.590s 1455.107us 50 50 100.00
hmac_test_hmac384_vectors 16.180s 2238.549us 60 60 100.00
hmac_test_hmac512_vectors 18.870s 797.432us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 40.300s 12591.221us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1026.250s 12705.464us 10 10 100.00
error 10 10 100.00
hmac_error 63.110s 18082.657us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 112.710s 42006.005us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.420s 2400.315us 10 10 100.00
hmac_long_msg 77.550s 23013.040us 10 10 100.00
hmac_back_pressure 77.720s 14699.464us 25 25 100.00
hmac_datapath_stress 1026.250s 12705.464us 10 10 100.00
hmac_burst_wr 40.300s 12591.221us 50 50 100.00
hmac_stress_all 2210.720s 334891.605us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.420s 2400.315us 10 10 100.00
hmac_long_msg 77.550s 23013.040us 10 10 100.00
hmac_back_pressure 77.720s 14699.464us 25 25 100.00
hmac_datapath_stress 1026.250s 12705.464us 10 10 100.00
hmac_wipe_secret 112.710s 42006.005us 10 10 100.00
hmac_test_sha256_vectors 264.270s 28989.002us 30 30 100.00
hmac_test_sha384_vectors 529.920s 57178.928us 75 75 100.00
hmac_test_sha512_vectors 518.700s 51727.670us 75 75 100.00
hmac_test_hmac256_vectors 15.590s 1455.107us 50 50 100.00
hmac_test_hmac384_vectors 16.180s 2238.549us 60 60 100.00
hmac_test_hmac512_vectors 18.870s 797.432us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.420s 2400.315us 10 10 100.00
hmac_long_msg 77.550s 23013.040us 10 10 100.00
hmac_back_pressure 77.720s 14699.464us 25 25 100.00
hmac_datapath_stress 1026.250s 12705.464us 10 10 100.00
hmac_burst_wr 40.300s 12591.221us 50 50 100.00
hmac_error 63.110s 18082.657us 10 10 100.00
hmac_wipe_secret 112.710s 42006.005us 10 10 100.00
hmac_test_sha256_vectors 264.270s 28989.002us 30 30 100.00
hmac_test_sha384_vectors 529.920s 57178.928us 75 75 100.00
hmac_test_sha512_vectors 518.700s 51727.670us 75 75 100.00
hmac_test_hmac256_vectors 15.590s 1455.107us 50 50 100.00
hmac_test_hmac384_vectors 16.180s 2238.549us 60 60 100.00
hmac_test_hmac512_vectors 18.870s 797.432us 75 75 100.00
hmac_stress_all 2210.720s 334891.605us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2210.720s 334891.605us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 14.565us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.950s 41.065us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.800s 260.066us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.800s 260.066us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.200s 20.890us 5 5 100.00
hmac_csr_rw 1.260s 45.937us 20 20 100.00
hmac_csr_aliasing 8.830s 836.936us 5 5 100.00
hmac_same_csr_outstanding 2.810s 458.244us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.200s 20.890us 5 5 100.00
hmac_csr_rw 1.260s 45.937us 20 20 100.00
hmac_csr_aliasing 8.830s 836.936us 5 5 100.00
hmac_same_csr_outstanding 2.810s 458.244us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.210s 428.730us 5 5 100.00
hmac_tl_intg_err 4.240s 1681.422us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.240s 1681.422us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.420s 2400.315us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.540s 479.925us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 400.520s 5781.685us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.130s 27.207us 1 1 100.00

Error Messages

   Test seed line log context