Simulation Results: keymgr

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.95 %
  • code
  • 98.98 %
  • assert
  • 97.72 %
  • func
  • 91.16 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.18 %
  • toggle
  • 98.60 %
  • FSM
  • 100.00 %
Validation stages
V1
99.44%
V2
99.40%
V2S
99.32%
V3
66.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
keymgr_smoke 18.910s 4835.103us 49 50 98.00
random 50 50 100.00
keymgr_random 65.170s 8295.506us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.240s 129.450us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 10.870s 1285.027us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 8.010s 1309.597us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.040s 65.460us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
keymgr_csr_aliasing 8.010s 1309.597us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 91.230s 13697.041us 49 50 98.00
sideload 200 200 100.00
keymgr_sideload 43.020s 3204.453us 50 50 100.00
keymgr_sideload_kmac 41.390s 3592.334us 50 50 100.00
keymgr_sideload_aes 35.920s 5388.181us 50 50 100.00
keymgr_sideload_otbn 29.740s 1253.081us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 21.000s 8650.718us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 6.230s 1105.148us 48 50 96.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 15.350s 643.104us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 50.990s 5511.712us 50 50 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 30.660s 4114.050us 49 50 98.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 15.350s 653.504us 50 50 100.00
stress_all 49 50 98.00
keymgr_stress_all 428.070s 213482.803us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.020s 18.176us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.300s 19.132us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.630s 631.802us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.630s 631.802us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.240s 129.450us 5 5 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
keymgr_csr_aliasing 8.010s 1309.597us 5 5 100.00
keymgr_same_csr_outstanding 2.900s 90.192us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.240s 129.450us 5 5 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
keymgr_csr_aliasing 8.010s 1309.597us 5 5 100.00
keymgr_same_csr_outstanding 2.900s 90.192us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
keymgr_tl_intg_err 7.900s 300.135us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.790s 423.572us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.790s 423.572us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.790s 423.572us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.790s 423.572us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.210s 589.216us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.900s 300.135us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.790s 423.572us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 91.230s 13697.041us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 65.170s 8295.506us 50 50 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 65.170s 8295.506us 50 50 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 65.170s 8295.506us 50 50 100.00
keymgr_csr_rw 1.210s 81.911us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 6.230s 1105.148us 48 50 96.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 30.660s 4114.050us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 30.660s 4114.050us 49 50 98.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 65.170s 8295.506us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 20.130s 717.990us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 30.710s 1287.338us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 6.230s 1105.148us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 30.710s 1287.338us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 30.710s 1287.338us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 30.710s 1287.338us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.820s 4846.957us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 30.710s 1287.338us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 33 50 66.00
keymgr_stress_all_with_rand_reset 28.130s 2205.188us 33 50 66.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 35851594110444201170135951872224509531979335341969859918192634319860421722316 94
UVM_ERROR @ 845790288 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 845790288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 9089157250690511440802710751272905082949026433246470767959538032429174736366 374
UVM_ERROR @ 1135610465 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1135610465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103410766636673402068115262642763874715006608401244713528955571866396847773040 1360
UVM_ERROR @ 1755884963 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1755884963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87232853101457756984641302811316582881625942256675779081120178224878906613217 250
UVM_ERROR @ 562927902 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 562927902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21896604116388103608480961965021165552910488102085224078411579647001666376615 291
UVM_ERROR @ 452807720 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 452807720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100284702821478193164478947313987186920485218045666348644164239702425402361086 689
UVM_ERROR @ 564394458 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 564394458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 55127344590220666506258595257302559372085176993109514316542225216703301173848 368
UVM_ERROR @ 2499448386 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2499448386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 10998558366132843005962175526330754183593444123299198502468260484882354714647 135
UVM_ERROR @ 103125618 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 103125618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26127721981760760517821114480285725307667504918734794953837193612510055490725 1635
UVM_ERROR @ 1795595615 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1795595615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17631638997378208241459881870407969008098480283720812905284028183379933153031 1145
UVM_ERROR @ 1600068118 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1600068118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65531810784964131365933127805323890461527623102414666391393766902141804867436 268
UVM_ERROR @ 464041257 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 464041257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 3416292719782637531809029616435472884519857038669887994197473558752012167090 706
UVM_ERROR @ 643294632 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 643294632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1485480825656473623975591460489954084809826025905198875448969641526553529486 426
UVM_ERROR @ 117949231 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 117949231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 5484446792658248183644407111389805778629186441348422018042782450317066029544 507
UVM_ERROR @ 903181973 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 903181973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85631148079745061214753127027938622144320931199627257365954312612657322246740 489
UVM_ERROR @ 429960417 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 429960417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65580806873471327705564110167827088217587907980096287037104388646576561595026 176
UVM_ERROR @ 110368549 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110368549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95107599732915768385041712835090117602834156391633889624457031495649999057197 154
UVM_ERROR @ 194977749 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 194977749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 62107370425356254620874749119874200174724038342116390566904628975161404827633 898
UVM_ERROR @ 1149613214 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 1149613214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_hwsw_invalid_input 75475653008507423184447742722164222509471467081292262186638468134614818167625 140
UVM_ERROR @ 55004656 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 55004656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_smoke 20136524015575169145430624067094053696105978514284512210964211242488539136942 96
UVM_ERROR @ 12964800 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 12964800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 31121359794258995472440064776215597382373474456290945970612668556869106749312 307
UVM_ERROR @ 14137451 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 14137451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*])
keymgr_lc_disable 58921110523560700250014881014545483077860066133679295521871818808220586255765 87
UVM_ERROR @ 58501324 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
UVM_INFO @ 58501324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
keymgr_lc_disable 54091936324359621725075541764087119868065826431955423985116808523235356754163 367
UVM_ERROR @ 564591698 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
UVM_INFO @ 564591698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---