Simulation Results: keymgr_dpe

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.37 %
  • code
  • 84.29 %
  • assert
  • 97.64 %
  • func
  • 17.18 %
  • line
  • 97.62 %
  • branch
  • 94.61 %
  • cond
  • 90.39 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
98.46%
V2
99.17%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
keymgr_dpe_smoke 221.780s 19219.831us 49 50 98.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.080s 33.676us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.080s 93.960us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 7.410s 599.975us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 6.130s 229.931us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.570s 26.227us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.080s 93.960us 20 20 100.00
keymgr_dpe_csr_aliasing 6.130s 229.931us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 0.860s 21.044us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.330s 29.613us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 3.500s 144.287us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 3.500s 144.287us 20 20 100.00
tl_d_outstanding_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.080s 33.676us 5 5 100.00
keymgr_dpe_csr_rw 1.080s 93.960us 20 20 100.00
keymgr_dpe_csr_aliasing 6.130s 229.931us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.360s 128.086us 19 20 95.00
tl_d_partial_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.080s 33.676us 5 5 100.00
keymgr_dpe_csr_rw 1.080s 93.960us 20 20 100.00
keymgr_dpe_csr_aliasing 6.130s 229.931us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.360s 128.086us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 5.520s 452.157us 20 20 100.00
keymgr_dpe_sec_cm 48.500s 3390.932us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.290s 105.966us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.290s 105.966us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.290s 105.966us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.290s 105.966us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 6.330s 676.621us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 48.500s 3390.932us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 48.500s 3390.932us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: *
keymgr_dpe_csr_mem_rw_with_rand_reset 18110715301930142329335015853928949433216163222901699264246389413979456466789 94
UVM_ERROR @ 26227042 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 26227042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
keymgr_dpe_same_csr_outstanding 31540054348445175795186084765159346076290968191864615877171432681391414727826 77
UVM_ERROR @ 1810490 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xd3bcd9d0 read out mismatch
UVM_INFO @ 1810490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_dpe_smoke 37995803426528988920068103101017648152054410008044057774565405288281493411430 4375
UVM_ERROR @ 3968231471 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 3968231471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---