Simulation Results: kmac

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 94.36 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.49 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
99.52%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 83.520s 18769.080us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.360s 55.732us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.420s 149.007us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.100s 5538.023us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.080s 2377.011us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.930s 287.155us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.420s 149.007us 20 20 100.00
kmac_csr_aliasing 7.080s 2377.011us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.000s 35.324us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.930s 77.277us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3825.230s 134101.251us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1331.250s 38895.164us 50 50 100.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 2092.880s 430912.849us 5 5 100.00
kmac_test_vectors_sha3_256 2204.240s 95522.671us 5 5 100.00
kmac_test_vectors_sha3_384 1656.420s 248137.757us 5 5 100.00
kmac_test_vectors_sha3_512 1154.480s 189030.734us 5 5 100.00
kmac_test_vectors_shake_128 208.770s 61284.355us 5 5 100.00
kmac_test_vectors_shake_256 2119.550s 90730.190us 4 5 80.00
kmac_test_vectors_kmac 3.790s 147.780us 5 5 100.00
kmac_test_vectors_kmac_xof 3.540s 384.520us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 449.710s 31015.134us 50 50 100.00
app 50 50 100.00
kmac_app 393.940s 119980.614us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 324.930s 49076.762us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 451.450s 398911.398us 50 50 100.00
error 49 50 98.00
kmac_error 419.050s 92628.622us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 16.710s 3739.265us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.930s 465.697us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 52.770s 2328.409us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.000s 2489.994us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 89.340s 7682.165us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 44.180s 1885.788us 50 50 100.00
stress_all 48 50 96.00
kmac_stress_all 4090.310s 478117.368us 48 50 96.00
intr_test 50 50 100.00
kmac_intr_test 1.190s 29.279us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 226.563us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.150s 1134.764us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.150s 1134.764us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.360s 55.732us 5 5 100.00
kmac_csr_rw 1.420s 149.007us 20 20 100.00
kmac_csr_aliasing 7.080s 2377.011us 5 5 100.00
kmac_same_csr_outstanding 2.180s 1101.766us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.360s 55.732us 5 5 100.00
kmac_csr_rw 1.420s 149.007us 20 20 100.00
kmac_csr_aliasing 7.080s 2377.011us 5 5 100.00
kmac_same_csr_outstanding 2.180s 1101.766us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.080s 173.116us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.080s 173.116us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.080s 173.116us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.080s 173.116us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.240s 1096.316us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.200s 1963.526us 20 20 100.00
kmac_sec_cm 107.990s 8313.629us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.200s 1963.526us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 44.180s 1885.788us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 83.520s 18769.080us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 449.710s 31015.134us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.080s 173.116us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 107.990s 8313.629us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 107.990s 8313.629us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 107.990s 8313.629us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 83.520s 18769.080us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 44.180s 1885.788us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 107.990s 8313.629us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 331.270s 35210.163us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 83.520s 18769.080us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 260.440s 4638.296us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_shake_256 32326963847584406354366801326856925194519977350428570817620089772090411723841 75
UVM_ERROR @ 79485133 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 79485133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 8043553801867290143662376848834219789696876781620424545277215851488895273437 202
UVM_ERROR @ 67864872637 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 67864872637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 108000211392701022603862241478191842720321576115480832169055486133178323264699 124
UVM_ERROR @ 5611650118 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 5611650118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 106234061300105705016561738101509633874693819434603173551307545914802264883260 207
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---