Simulation Results: kmac

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 92.34 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.45%
V2S
99.60%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 70.770s 18233.355us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.250s 42.906us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.600s 32.874us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.690s 2934.299us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.400s 533.980us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.210s 350.485us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.600s 32.874us 20 20 100.00
kmac_csr_aliasing 7.400s 533.980us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.970s 13.732us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.620s 34.296us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3233.890s 1880119.582us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 916.460s 454804.989us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1891.630s 457236.688us 5 5 100.00
kmac_test_vectors_sha3_256 1476.110s 238485.163us 5 5 100.00
kmac_test_vectors_sha3_384 1523.120s 68367.726us 5 5 100.00
kmac_test_vectors_sha3_512 881.220s 180008.235us 5 5 100.00
kmac_test_vectors_shake_128 2076.450s 359667.780us 5 5 100.00
kmac_test_vectors_shake_256 324.520s 89630.794us 5 5 100.00
kmac_test_vectors_kmac 3.120s 108.579us 5 5 100.00
kmac_test_vectors_kmac_xof 2.940s 99.305us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 389.940s 19610.103us 50 50 100.00
app 50 50 100.00
kmac_app 315.140s 12854.793us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 294.260s 18795.253us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 248.570s 20455.289us 50 50 100.00
error 50 50 100.00
kmac_error 411.380s 89298.708us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 16.520s 15627.304us 50 50 100.00
sideload_invalid 37 50 74.00
kmac_sideload_invalid 122.840s 10123.387us 37 50 74.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.760s 4235.128us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 34.790s 1323.571us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 56.570s 23774.080us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 45.410s 3116.252us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2220.210s 83105.047us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.150s 28.082us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.180s 29.768us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.540s 640.395us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.540s 640.395us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.250s 42.906us 5 5 100.00
kmac_csr_rw 1.600s 32.874us 20 20 100.00
kmac_csr_aliasing 7.400s 533.980us 5 5 100.00
kmac_same_csr_outstanding 3.710s 2346.446us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.250s 42.906us 5 5 100.00
kmac_csr_rw 1.600s 32.874us 20 20 100.00
kmac_csr_aliasing 7.400s 533.980us 5 5 100.00
kmac_same_csr_outstanding 3.710s 2346.446us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 71.563us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.390s 71.563us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 71.563us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.390s 71.563us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 5.060s 3701.438us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.970s 1076.350us 20 20 100.00
kmac_sec_cm 69.610s 4987.112us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.970s 1076.350us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 45.410s 3116.252us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 70.770s 18233.355us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 389.940s 19610.103us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.390s 71.563us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 69.610s 4987.112us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 69.610s 4987.112us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 69.610s 4987.112us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 70.770s 18233.355us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 45.410s 3116.252us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 69.610s 4987.112us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 9 10 90.00
kmac_mubi 268.060s 200000.000us 9 10 90.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 70.770s 18233.355us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 182.490s 23192.691us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: *
kmac_shadow_reg_errors_with_csr_rw 95527041931204702501514909123801777508588761304062302500335983977339127525141 165
UVM_ERROR @ 41309155 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (123 [0x7b] vs 959 [0x3bf]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
UVM_INFO @ 41309155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 92264334362917175292000076892196630494334019088799342531241242950699015657875 76
UVM_FATAL @ 10023370977 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1376a000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10023370977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 97656914047596348397373728333715579126737757526265991362550083232219344204795 77
UVM_FATAL @ 10130898899 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xba1a000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10130898899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_mubi 104254417216118929225807061947877839183271363066379173799138027854840637776028 203
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 88911661776665606237588937363986163274151317212817951125390924329888456728306 244
UVM_ERROR @ 8167067300 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8167067300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 105661743473325381747477274226954176518977733050776617562391762737571122858587 205
UVM_ERROR @ 11714792721 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11714792721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 69473118611597333105279945975542572373737888616518794017433929837407634487631 97
UVM_ERROR @ 1395584663 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1395584663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 100119765318547109238891067898943515343940319584369296517509928120370148388123 84
UVM_FATAL @ 10359787897 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x11291000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10359787897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 76366748690425274483463930741921103874751507200087067516186514379219103342933 86
UVM_FATAL @ 10127263957 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1810e000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10127263957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 19069659950087021556238577967126817502925048839201053873629570124054272549865 85
UVM_FATAL @ 10265375951 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe409e000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10265375951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 86384484400168156459417614011222530027338476687095084550494057681373364444305 75
UVM_FATAL @ 10020000953 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x15d67000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10020000953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 37711243783156710846824175350352124971439866972352821770449277746484753956785 75
UVM_FATAL @ 10090105722 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b844000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10090105722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 51923892135504349384308651122903819046040849711798363019479036451979356430451 75
UVM_FATAL @ 10019506527 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7907a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10019506527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 34922194283584143683837413156026074152603985810951641094434194281656399621780 75
UVM_FATAL @ 10039676593 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe6ce2000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10039676593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 40906643261362582112634543548799586388692918583152602227962904217133123637505 94
UVM_FATAL @ 10638899491 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x53765000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10638899491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 92991781213075896076608838648202100766878330952571289753137513010878573691191 80
UVM_FATAL @ 10043600339 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6a4f8000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10043600339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23)
kmac_sideload_invalid 41309297114090169727910799570469090140076263301575254225533547208914233812061 97
UVM_FATAL @ 10123387236 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x35bf5000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10123387236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 69642452298665465364757438162492006094474865212173221177898218734876684407334 87
UVM_FATAL @ 10597508103 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x754fa000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10597508103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---