Simulation Results: mbx

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.89 %
  • code
  • 90.31 %
  • assert
  • 97.01 %
  • func
  • 85.35 %
  • block
  • 95.53 %
  • line
  • 95.98 %
  • branch
  • 88.83 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
98.01%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 85.000s 22211.705us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 14.296us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 13.379us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 5.000s 1016.697us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 46.779us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 165.848us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 13.379us 20 20 100.00
mbx_csr_aliasing 2.000s 46.779us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 2 50.00
mbx_stress 168.000s 11235.134us 1 2 50.00
mbx_max_activity 0 2 0.00
mbx_stress_zero_delays 31.000s 143.777us 0 2 0.00
mbx_imbx_oob 0 2 0.00
mbx_imbx_oob 34.000s 1011.509us 0 2 0.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 36.000s 1478.268us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 28.000s 52.657us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 2.000s 19.246us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 6.000s 208.548us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 6.000s 208.548us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 14.296us 5 5 100.00
mbx_csr_rw 2.000s 13.379us 20 20 100.00
mbx_csr_aliasing 2.000s 46.779us 5 5 100.00
mbx_same_csr_outstanding 2.000s 51.087us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 14.296us 5 5 100.00
mbx_csr_rw 2.000s 13.379us 20 20 100.00
mbx_csr_aliasing 2.000s 46.779us 5 5 100.00
mbx_same_csr_outstanding 2.000s 51.087us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 28.000s 25.879us 5 5 100.00
mbx_tl_intg_err 3.000s 828.660us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 25817923475614321910509768577194452874280364469331990050450559375083843853755 102
UVM_ERROR @ 143777272 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (2987478809 [0xb2114f19] vs 1856281050 [0x6ea499da]) RDATA read data mismatched
UVM_INFO @ 143777272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 1030473274647068025647573208706627497796532215067556661496889308544494726893 359
UVM_ERROR @ 933240375 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 3234978542 [0xc0d1daee]) RDATA read data mismatched
UVM_INFO @ 933240375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_imbx_oob 101476507346642940507853649667121020868642756443970829680673905971570763094928 96
UVM_ERROR @ 1011509047 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 1011509047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 63712142294835562790970983877353368143380925310299412612827039223781875559958 102
UVM_ERROR @ 952068194 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 952068194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress 10231043273603376601195969466862665024880146982709344757250922853317477051526 195
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 105228738 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 105228738 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 105228738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---