Simulation Results: otbn

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 96.40 %
  • assert
  • 89.83 %
  • func
  • 100.00 %
  • block
  • 99.54 %
  • line
  • 99.65 %
  • branch
  • 94.62 %
  • toggle
  • 93.90 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
99.42%
V2S
99.32%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 75.901us 1 1 100.00
single_binary 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 9.000s 35.645us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 31.211us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 9.000s 139.709us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 23.950us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 40.921us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 31.211us 20 20 100.00
otbn_csr_aliasing 4.000s 23.950us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 36.000s 1733.398us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 20.000s 3549.887us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 41.000s 121.384us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 54.000s 199.770us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 87.000s 1643.310us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 98.000s 847.320us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 100.000s 894.934us 59 60 98.33
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 8.000s 56.519us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 13.000s 248.296us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 59.514us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 7.000s 28.522us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 7.000s 144.046us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 7.000s 144.046us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 9.000s 35.645us 5 5 100.00
otbn_csr_rw 8.000s 31.211us 20 20 100.00
otbn_csr_aliasing 4.000s 23.950us 5 5 100.00
otbn_same_csr_outstanding 5.000s 25.613us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 9.000s 35.645us 5 5 100.00
otbn_csr_rw 8.000s 31.211us 20 20 100.00
otbn_csr_aliasing 4.000s 23.950us 5 5 100.00
otbn_same_csr_outstanding 5.000s 25.613us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 42.205us 10 10 100.00
otbn_dmem_err 14.000s 38.554us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 37.000s 584.436us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 28.331us 5 5 100.00
otbn_mac_bignum_acc_err 16.208s 0.000us 4 5 80.00
otbn_urnd_err 7.000s 17.282us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 156.155us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 68.925us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 11.000s 836.106us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
otbn_tl_intg_err 32.000s 194.621us 20 20 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 42.000s 263.112us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 75.901us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 14.000s 38.554us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 42.205us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 32.000s 194.621us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 100.000s 894.934us 59 60 98.33
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 42.205us 10 10 100.00
otbn_dmem_err 14.000s 38.554us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 56.519us 4 5 80.00
otbn_illegal_mem_acc 7.000s 156.155us 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 42.205us 10 10 100.00
otbn_dmem_err 14.000s 38.554us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 56.519us 4 5 80.00
otbn_illegal_mem_acc 7.000s 156.155us 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 100.000s 894.934us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 42.205us 10 10 100.00
otbn_dmem_err 14.000s 38.554us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 56.519us 4 5 80.00
otbn_illegal_mem_acc 7.000s 156.155us 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 540.275us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 25.709us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 433.000s 1637.367us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 433.000s 1637.367us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 18.000s 64.858us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 64.401us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 35.000s 708.779us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 35.000s 708.779us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 9.000s 34.815us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 87.000s 1643.310us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 22.000s 68.067us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 47.000s 614.161us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 508.000s 2236.526us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 495.000s 1391.656us 5 10 50.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_mac_bignum_acc_err 68276215116677762022046509068755818089778128598961776358049309577716653501591 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 68276215116677762022046509068755818089778128598961776358049309577716653501591 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3580243095 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_mac_bignum_acc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_mac_bignum_acc_err.3580243095 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_mac_bignum_acc_err.3580243095 -covoverwrite' seed=68276215116677762022046509068755818089778128598961776358049309577716653501591 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_mac_bignum_acc_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 68276215116677762022046509068755818089778128598961776358049309577716653501591 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest
2026/01/10 05:31:05 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 34438732064021289829763677061726348101575712154009503745455258057029730860237 245
UVM_FATAL @ 1151638583 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1151638583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 69449340676263141635219654042926891408887582655912695778150463713783575971861 413
UVM_FATAL @ 969644004 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 969644004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_zero_state_err_urnd 79721899548434860621422734329613834532989323241391603585281259612139000453030 105
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 135906624 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 135906624 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 135906624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 71856021149222524523645772580357099232786833951555210762285352117348207730869 338
UVM_ERROR @ 1391656216 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1391656216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 66534055387965740428498914052142643647170256661282054277492746802651306808129 380
UVM_ERROR @ 1124207007 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1124207007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 112495902824202953712518796283526655132660451778369912179693769589218504041021 375
UVM_ERROR @ 1767201343 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1767201343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 71627006220374908104765814291587608550785851824019926996802489706964424483317 111
UVM_ERROR @ 6950588 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (0 [0x0] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 6950588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_escalate 7198245885948499207936127372282246578345886216827801901078716374786026760089 110
UVM_FATAL @ 190678030 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 190678030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 3585316671852593920057964321420146201885863089205109136554425708371749370130 83
UVM_FATAL @ 1464809 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 1464809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 43358583865072419718239016275863427755018690938288090636129586708074599073262 148
UVM_FATAL @ 110757180 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 110757180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---