Simulation Results: rom_ctrl

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
89.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.720s 256.565us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 6.660s 2108.082us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.180s 170.363us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.640s 173.216us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.500s 560.920us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.510s 180.015us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.180s 170.363us 20 20 100.00
rom_ctrl_csr_aliasing 5.500s 560.920us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.660s 127.265us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.860s 561.324us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.290s 304.546us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 21.840s 2189.455us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.810s 314.153us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 7.780s 549.811us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 9.660s 353.778us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 9.660s 353.778us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.660s 2108.082us 5 5 100.00
rom_ctrl_csr_rw 6.180s 170.363us 20 20 100.00
rom_ctrl_csr_aliasing 5.500s 560.920us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.960s 4186.969us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.660s 2108.082us 5 5 100.00
rom_ctrl_csr_rw 6.180s 170.363us 20 20 100.00
rom_ctrl_csr_aliasing 5.500s 560.920us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.960s 4186.969us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.650s 3064.277us 20 20 100.00
tl_intg_err 21 25 84.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
rom_ctrl_tl_intg_err 55.100s 5104.768us 20 20 100.00
prim_fsm_check 1 5 20.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
prim_count_check 1 5 20.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_compare_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.720s 256.565us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.720s 256.565us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.720s 256.565us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 55.100s 5104.768us 20 20 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
rom_ctrl_kmac_err_chk 7.810s 314.153us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 116.050s 7771.253us 19 20 95.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.650s 3064.277us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 210.460s 2077.066us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 455.900s 5146.348us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 68012719969491341345635338490908355161156713789795084482518898693096729293279 120
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 23380276ps failed at 23380276ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 30514978ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 30514978ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 85942095276499701933009784201192361582054015635413884120651387406827384858663 544
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 151405533ps failed at 151405533ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 151405533ps failed at 151405533ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 6982442417632829103541927667089650759263441286236348275557604086673027509045 228
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 11936030ps failed at 11936030ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11936030ps failed at 11936030ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 41435758784477871481655449562072979623818333266369510806928591783617006934452 95
UVM_ERROR @ 4758523055 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 4758523055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 71094580335832328611134002497192792673443921783042540087694521898333249749701 176
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 23654230ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 23654230ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 23654230ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))