rom_ctrl Simulation Results

Simulation Results: rom_ctrl

09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.53%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	8.770s	228.774us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	19.410s	1049.107us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	10.500s	292.753us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	12.480s	304.400us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	11.800s	289.580us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	11.690s	312.507us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	10.500s	292.753us	20	20	100.00
	rom_ctrl_csr_aliasing	11.800s	289.580us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	11.860s	294.665us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	11.900s	291.861us	5	5	100.00

213/214 passed

99.53 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	10.450s	575.664us	2	2	100.00
stress_all				19	20	95.00
	rom_ctrl_stress_all	42.580s	1228.554us	19	20	95.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	18.280s	1038.953us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	15.900s	2084.144us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	15.450s	295.321us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	15.450s	295.321us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	19.410s	1049.107us	5	5	100.00
	rom_ctrl_csr_rw	10.500s	292.753us	20	20	100.00
	rom_ctrl_csr_aliasing	11.800s	289.580us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.080s	992.954us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	19.410s	1049.107us	5	5	100.00
	rom_ctrl_csr_rw	10.500s	292.753us	20	20	100.00
	rom_ctrl_csr_aliasing	11.800s	289.580us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.080s	992.954us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	52.600s	3095.298us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00
	rom_ctrl_tl_intg_err	130.320s	1216.782us	20	20	100.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	8.770s	228.774us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	8.770s	228.774us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	8.770s	228.774us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	130.320s	1216.782us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
	rom_ctrl_kmac_err_chk	18.280s	1038.953us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	228.690s	7396.920us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	52.600s	3095.298us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	622.330s	2897.158us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	275.690s	4143.029us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	10748652382177584559341998669381700530624732503081512896681415344333572161016	114	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 16491930ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 16491930ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 16491930ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	66740373416365917355612473362855641829555630276398371216699542416229154976848	296	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 124608002ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 124608002ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 124608002ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	48576982216470966015474328338867932397486857963084270241519957047060854282480	302	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 43078982ps failed at 43078982ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 43078982ps failed at 43078982ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	24234020037557196527315473032577914938317878039839459658243912710665820015729	221	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 29351128ps failed at 29351128ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29351128ps failed at 29351128ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
	rom_ctrl_stress_all	75330757797626877744688688719627770490355071410262366500485419128380854134121	77	UVM_ERROR @ 3104625488 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire UVM_INFO @ 3104625488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---