Simulation Results: rstmgr

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.56 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.32 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.510s 68.783us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.070s 93.528us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.950s 195.977us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.270s 52.675us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.620s 99.251us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00
rstmgr_csr_aliasing 1.270s 52.675us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.850s 191.845us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.150s 41.178us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.300s 73.023us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 5.780s 828.217us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 5.780s 828.217us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 5.780s 828.217us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 5.780s 828.217us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 33.990s 5428.393us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.210s 97.375us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.340s 88.230us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.340s 88.230us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.070s 93.528us 5 5 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00
rstmgr_csr_aliasing 1.270s 52.675us 5 5 100.00
rstmgr_same_csr_outstanding 1.160s 73.970us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.070s 93.528us 5 5 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00
rstmgr_csr_aliasing 1.270s 52.675us 5 5 100.00
rstmgr_same_csr_outstanding 1.160s 73.970us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 23.320s 4715.666us 5 5 100.00
rstmgr_tl_intg_err 5.260s 855.431us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 23.320s 4715.666us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 23.320s 4715.666us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 5.260s 855.431us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.410s 61.656us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 3.910s 466.235us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 2.170s 291.320us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 23.320s 4715.666us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.010s 36.743us 20 20 100.00

Error Messages

   Test seed line log context