rstmgr_cnsty_chk Simulation Results

Simulation Results: rstmgr_cnsty_chk

09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

80.00%

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	rstmgr_cnsty_chk_test	3.000s	9429.340us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	33498852685731598843406233775170571467647245960399586696199244416987591264648	172	UVM_ERROR @ 1909318857 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1928518857 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1947718857 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1966918857 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1986118857 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	13419977537529583391381127503118401656971175816662317332320878295647129657956	172	UVM_ERROR @ 1782364411 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1800284411 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1818204411 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1836124411 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1854044411 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16