Simulation Results: spi_host

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.47%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 134.000s 7652.041us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 23.380us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 107.951us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 240.756us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 29.278us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 80.874us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 107.951us 20 20 100.00
spi_host_csr_aliasing 2.000s 29.278us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 38.743us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 16.817us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 31.000s 29.090us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 40.000s 1536.701us 50 50 100.00
spi_host_error_cmd 31.000s 25.193us 50 50 100.00
spi_host_event 225.000s 28391.145us 50 50 100.00
clock_rate 49 50 98.00
spi_host_speed 31.000s 22.263us 49 50 98.00
speed 49 50 98.00
spi_host_speed 31.000s 22.263us 49 50 98.00
chip_select_timing 49 50 98.00
spi_host_speed 31.000s 22.263us 49 50 98.00
sw_reset 50 50 100.00
spi_host_sw_reset 98.000s 6823.228us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 31.000s 41.069us 50 50 100.00
cpol_cpha 49 50 98.00
spi_host_speed 31.000s 22.263us 49 50 98.00
full_cycle 49 50 98.00
spi_host_speed 31.000s 22.263us 49 50 98.00
duplex 50 50 100.00
spi_host_smoke 134.000s 7652.041us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 134.000s 7652.041us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 126.000s 12229.392us 50 50 100.00
spien 50 50 100.00
spi_host_spien 93.000s 7031.718us 50 50 100.00
stall 49 50 98.00
spi_host_status_stall 810.000s 21209.326us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 32.000s 51.418us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 40.000s 1536.701us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 31.000s 68.295us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 3.000s 15.374us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 106.828us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 106.828us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 23.380us 5 5 100.00
spi_host_csr_rw 2.000s 107.951us 20 20 100.00
spi_host_csr_aliasing 2.000s 29.278us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 159.532us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 23.380us 5 5 100.00
spi_host_csr_rw 2.000s 107.951us 20 20 100.00
spi_host_csr_aliasing 2.000s 29.278us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 159.532us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 31.000s 717.745us 5 5 100.00
spi_host_tl_intg_err 3.000s 91.401us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 91.401us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 492.000s 13167.433us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_speed 89722811219331574975766748256400485268949966232928170092008676557282309891404 223
UVM_FATAL @ 10066202890 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x65910994, Comparison=CompareOpEq, exp_data=0x0, call_count=32
UVM_INFO @ 10066202890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 75220306837174743791473663050744576712932301468513370901303578494630875500793 3912
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---