Simulation Results: sram_ctrl

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.46%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 99.260s 2658.212us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.080s 58.786us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.040s 12.264us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.500s 123.421us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.080s 174.474us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.720s 3537.217us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.040s 12.264us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 174.474us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 359.290s 82683.548us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 180.470s 19575.570us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 942.940s 101095.850us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 370.790s 6254.094us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2474.210s 879334.663us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1213.490s 16702.334us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 138.940s 85880.026us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1219.070s 53586.178us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 91.030s 1842.685us 50 50 100.00
sram_ctrl_partial_access_b2b 538.560s 20412.919us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 101.870s 1547.341us 50 50 100.00
sram_ctrl_throughput_w_partial_write 106.520s 3243.554us 50 50 100.00
sram_ctrl_throughput_w_readback 101.690s 1906.773us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1272.420s 34148.445us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.230s 3728.355us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5214.720s 549506.461us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.070s 23.298us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.920s 157.944us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.920s 157.944us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 58.786us 5 5 100.00
sram_ctrl_csr_rw 1.040s 12.264us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 174.474us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.200s 90.342us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 58.786us 5 5 100.00
sram_ctrl_csr_rw 1.040s 12.264us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 174.474us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.200s 90.342us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 63.950s 25162.773us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
sram_ctrl_tl_intg_err 3.250s 515.140us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.250s 515.140us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1272.420s 34148.445us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1272.420s 34148.445us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.040s 12.264us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1219.070s 53586.178us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1219.070s 53586.178us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1219.070s 53586.178us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 138.940s 85880.026us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 48 50 96.00
sram_ctrl_mubi_enc_err 10.080s 4446.794us 48 50 96.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 63.950s 25162.773us 20 20 100.00
sec_cm_mem_readback 31 50 62.00
sram_ctrl_readback_err 10.720s 10959.176us 31 50 62.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 99.260s 2658.212us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 99.260s 2658.212us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1219.070s 53586.178us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 138.940s 85880.026us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 99.260s 2658.212us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.110s 25.279us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 124.760s 2027.597us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 48867589768888343161508108013646986507930821489503535863889479793324803737668 95
UVM_ERROR @ 1369412679 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x6d)
UVM_INFO @ 1369412679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 85430007456597413614901522722833956056064706810476083289528351545957241366475 95
UVM_ERROR @ 2735864088 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xa) != exp (0x4a)
UVM_INFO @ 2735864088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 32229879345385286663809267471718217045109951790628768860194968151878347533198 95
UVM_ERROR @ 2991388966 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x68) != exp (0x3f)
UVM_INFO @ 2991388966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 37953746656042847928762326555311691449876041006415606815314997197292449310542 95
UVM_ERROR @ 657170043 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x7)
UVM_INFO @ 657170043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 21808622784951496821744286429134083679079592865033451624697899546175862330612 95
UVM_ERROR @ 1361259653 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0xe)
UVM_INFO @ 1361259653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 31742441913056125409334495640814941080982083127088379301835014639709943951458 95
UVM_ERROR @ 10959176079 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x29) != exp (0x26)
UVM_INFO @ 10959176079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12623132163441440553513472911571730558767033943019062791181916392400941734485 95
UVM_ERROR @ 659136733 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x46) != exp (0x1a)
UVM_INFO @ 659136733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 95222189811286498926024633742022767490609022531055936600487018912683961166263 95
UVM_ERROR @ 794198202 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x50) != exp (0x7a)
UVM_INFO @ 794198202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 82016707513652552276906369847670474462735095730066933747426204643846440458109 95
UVM_ERROR @ 1368926070 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x68)
UVM_INFO @ 1368926070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 47795198377369162883970534756795926264993023716996962772010878538609357000773 95
UVM_ERROR @ 6570586584 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0xf)
UVM_INFO @ 6570586584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 95291026869937106977729034754440250869661555424969275664569802790012257741812 95
UVM_ERROR @ 1352979739 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x5a)
UVM_INFO @ 1352979739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 14394103754852948359010745588780788169862128995900537325910245849034057736861 95
UVM_ERROR @ 2739154449 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x15) != exp (0x4b)
UVM_INFO @ 2739154449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 38448811813125260744301789700263925480510476073548601950375635447729441454404 95
UVM_ERROR @ 674251538 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0x5a)
UVM_INFO @ 674251538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 77671058626727414890445091219962212910992369740904745311510926098073426424281 95
UVM_ERROR @ 1777994371 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1) != exp (0x49)
UVM_INFO @ 1777994371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36054809849065843619145022392342101376674747215723129314258825640656746172576 95
UVM_ERROR @ 3870374571 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x7c)
UVM_INFO @ 3870374571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 4178619293093718996136408870711969795300979472483975821887537111377916341369 95
UVM_ERROR @ 1315629686 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x58) != exp (0xa)
UVM_INFO @ 1315629686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30508565936063499408821921241690946333662997956975471176346592963082099898873 95
UVM_ERROR @ 671402768 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x72)
UVM_INFO @ 671402768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 23369783232036923894789707334799386493835854474561048001394029943083024970986 95
UVM_ERROR @ 2738971329 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x4b)
UVM_INFO @ 2738971329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 831055482329395357525676187445302701013376008282259164222313163227122045189 96
UVM_ERROR @ 1708333 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1708333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 44222967551897411156913039554399378254397079101522118305356770194628832124632 96
UVM_ERROR @ 4936627 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4936627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 83145208383620820899778312645639311203376360286500156557089917868872638905356 98
UVM_ERROR @ 25279005 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 25279005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 42823897343641901931149551966591863023255497275804102616521740539012600638896 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 4690999855 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 4690999855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 24931051155994963315125782834386458142636975203557600415286932893800438643827 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 869294181 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 869294181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 30918925212508529964126629065352845857325471884540026910808956617420274794350 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1201757 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1201757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 18712583030070861004699664422480220968870155597289634179158221168366215436154 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 5107938 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5107938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3510) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_readback_err 90489278116319592013538938449676746718017799902565340546495634173779041911735 95
UVM_ERROR @ 1335009322 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3510) { a_addr: 'hde9beba8 a_data: 'hf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb9 a_opcode: 'h0 a_user: 'h27e32 d_param: 'h0 d_source: 'hb9 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1335009322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---