Simulation Results: sram_ctrl

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.57%
V2
100.00%
V2S
93.21%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 94.800s 1298.823us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.990s 19.198us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.020s 40.868us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.440s 185.269us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.030s 152.933us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 12.220s 10004.786us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.020s 40.868us 20 20 100.00
sram_ctrl_csr_aliasing 1.030s 152.933us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 12.810s 874.455us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 6.710s 167.235us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1286.360s 62696.624us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 373.060s 7865.990us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 82.780s 16635.857us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1289.090s 4879.388us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 12.410s 1870.697us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1355.790s 29338.031us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 104.410s 219.140us 50 50 100.00
sram_ctrl_partial_access_b2b 510.620s 289221.494us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 94.450s 419.868us 50 50 100.00
sram_ctrl_throughput_w_partial_write 101.890s 178.946us 50 50 100.00
sram_ctrl_throughput_w_readback 101.430s 609.982us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1236.970s 16703.367us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.190s 36.302us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 4104.780s 265267.129us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.040s 45.584us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.570s 149.642us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.570s 149.642us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.990s 19.198us 5 5 100.00
sram_ctrl_csr_rw 1.020s 40.868us 20 20 100.00
sram_ctrl_csr_aliasing 1.030s 152.933us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.100s 75.509us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.990s 19.198us 5 5 100.00
sram_ctrl_csr_rw 1.020s 40.868us 20 20 100.00
sram_ctrl_csr_aliasing 1.030s 152.933us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.100s 75.509us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 4.820s 972.756us 19 20 95.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
sram_ctrl_tl_intg_err 3.110s 318.324us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.110s 318.324us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1236.970s 16703.367us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1236.970s 16703.367us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.020s 40.868us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1355.790s 29338.031us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1355.790s 29338.031us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1355.790s 29338.031us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 12.410s 1870.697us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 43 50 86.00
sram_ctrl_mubi_enc_err 1.520s 52.098us 43 50 86.00
sec_cm_mem_integrity 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 4.820s 972.756us 19 20 95.00
sec_cm_mem_readback 36 50 72.00
sram_ctrl_readback_err 1.620s 173.055us 36 50 72.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 94.800s 1298.823us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 94.800s 1298.823us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1355.790s 29338.031us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 12.410s 1870.697us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 94.800s 1298.823us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.950s 2.710us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
sram_ctrl_stress_all_with_rand_reset 809.080s 2858.409us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 50807860119875799561700485852389686334417274100826188484100069119911359635286 95
UVM_ERROR @ 91429876 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x79)
UVM_INFO @ 91429876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54321097585829117203521472348683753906965654181869948113580767597976433550702 95
UVM_ERROR @ 97800618 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x5f)
UVM_INFO @ 97800618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 42582073849570944033892630932775671254561671387613732289877829818928717250090 95
UVM_ERROR @ 115316352 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x43)
UVM_INFO @ 115316352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 85927904064241606951213276603678961776522996153579548663210685685267330038203 100
UVM_ERROR @ 75311764 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x9) != exp (0x14)
UVM_INFO @ 75311764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 2444123484996587227981733375101579673053837446852713372702899548031672763266 95
UVM_ERROR @ 87780865 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x21)
UVM_INFO @ 87780865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 1775992420379195791713780767013826953169087881488672117538803049630668002285 95
UVM_ERROR @ 24300952 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x6)
UVM_INFO @ 24300952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 10540207964377046687720453886962475173405926376800281697769689733929357571645 95
UVM_ERROR @ 131034924 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x1a)
UVM_INFO @ 131034924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 77687877321786771077746586705101290219863770341364679426187778676618112621659 95
UVM_ERROR @ 23753561 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x52)
UVM_INFO @ 23753561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 45604385505626550723112855885155372072901017684688646602438194742190561495757 95
UVM_ERROR @ 97376386 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x8) != exp (0x2c)
UVM_INFO @ 97376386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 37443369144706399240233764861755984219388022952418492347763085835621242991471 95
UVM_ERROR @ 28939008 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x68)
UVM_INFO @ 28939008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 41210206698222856289938335100446177416315764832866064773652766929255666417775 95
UVM_ERROR @ 87927878 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x69) != exp (0x62)
UVM_INFO @ 87927878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 101985285944861158120891415299706759979664311709218767403993078438117768582756 95
UVM_ERROR @ 108138986 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x53) != exp (0x39)
UVM_INFO @ 108138986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 55509342069029837918827934845473151489849093602998251110148124440979752304018 95
UVM_ERROR @ 61232789 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5c) != exp (0x47)
UVM_INFO @ 61232789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 43095339153465673145446391830367788222938505020879043157794235904437083978752 95
UVM_ERROR @ 94038717 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x10)
UVM_INFO @ 94038717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 36895463827609735196069419747620705667878733228451512430405007561167893516714 97
UVM_ERROR @ 2403352 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2403352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 111952112760208034093449400556618989814038519633858856179017449168340385040279 96
UVM_ERROR @ 22423489 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 22423489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 65419510934514622303767543114103816698571793172451878232461594951736396892618 98
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4636455ps failed at 4636455ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 5516692 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5516692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 75792188693110893455248463631871238708493849306516467823879386022720712298160 97
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 4169498 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4169498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 95187909737312169395037366343655429412719617487517445091237551742842482084890 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 436001800 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 436001800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 108784852071853725924019190916168444425888270086188814355469747310946281857252 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 35544524 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 35544524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 112510547096806122171568467984220841993426766945907130232213239252318442277669 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 51740432 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 51740432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 107800154466878869564249641791865542676691291622276029950567897363230337595722 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 26610197 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 26610197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 49252821350422956877563043191891617226168059573738002435973116752395070329522 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 50831908 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 50831908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 33358225195084368667746235416074544752976880477691854051238302944736052296314 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 90048313 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 90048313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 59555714071808834310192560949598770211479320895039716874759204014591266744733 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 90092067 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 90092067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 115576939376637384895595125992422242077758703271767127800876872715625620489321 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2709963 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2709963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 25841888217581619525570180126448543810242457331539305699671676754199638159089 123
UVM_ERROR @ 897593358 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 897593358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
sram_ctrl_passthru_mem_tl_intg_err 33903284433941184427300351051006843557297373317924898335550808752607439383156 120
UVM_ERROR @ 654766054 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 654766054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done
sram_ctrl_csr_mem_rw_with_rand_reset 8936200758244776038519543804345047569840435537386104727831304231854418333821 93
UVM_FATAL @ 10004785747 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
UVM_INFO @ 10004785747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---