ac_range_check Simulation Results

Simulation Results: ac_range_check

16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.28 %

code
93.54 %

assert
97.63 %

func
58.67 %

block
99.21 %

line
99.94 %

branch
98.35 %

toggle
82.34 %

Validation stages

V1		96.67%
V2		97.11%
V2S		100.00%
V3		100.00%
unmapped		100.00%

116/120 passed

96.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				19	20	95.00
	ac_range_check_smoke	66.000s	6703.635us	19	20	95.00
ac_range_check_smoke_racl				17	20	85.00
	ac_range_check_smoke_racl	77.000s	3473.202us	17	20	85.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	78.860us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	4.000s	134.133us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	59.000s	10228.144us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	30.000s	1103.540us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	3.000s	28.729us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	4.000s	134.133us	20	20	100.00
	ac_range_check_csr_aliasing	30.000s	1103.540us	5	5	100.00

302/311 passed

97.11 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	12.000s	55.127us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	33.000s	902.610us	1	1	100.00
stress_all				41	50	82.00
	ac_range_check_stress_all	348.000s	11999.530us	41	50	82.00
alert_test				50	50	100.00
	ac_range_check_alert_test	13.000s	58.472us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	3.000s	26.084us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	8.000s	179.299us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	8.000s	179.299us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	78.860us	5	5	100.00
	ac_range_check_csr_rw	4.000s	134.133us	20	20	100.00
	ac_range_check_csr_aliasing	30.000s	1103.540us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	1239.670us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	78.860us	5	5	100.00
	ac_range_check_csr_rw	4.000s	134.133us	20	20	100.00
	ac_range_check_csr_aliasing	30.000s	1103.540us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	1239.670us	20	20	100.00

V2S

125/125 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	27.000s	984.887us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	27.000s	984.887us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	27.000s	984.887us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	27.000s	984.887us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	129.000s	5132.547us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_sec_cm	24.000s	48.591us	5	5	100.00
	ac_range_check_tl_intg_err	16.000s	412.206us	20	20	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	475.000s	7002.698us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	51.000s	1483.864us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state
	ac_range_check_smoke_racl	17936359580368788113464378471986120538585977242953611844762946166081607973343	4517	UVM_ERROR @ 4220972396 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 4220972396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	25512630061760276424138790271450460307571591444038263728339812784599651760394	3993	UVM_ERROR @ 3288613074 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3288613074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	88610017154681472587074757768876520678800535703158958567297239170758106511646	4090	UVM_ERROR @ 4979061426 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 4979061426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	69130344997262447157636255783930724563547711229298988223663151110550083566667	8883	UVM_ERROR @ 3855556910 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3855556910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	26840166922670307567613435428186029197336860491786268597980661672556199246930	4285	UVM_ERROR @ 5033112548 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5033112548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke	111972104232324292425371571570313778442233380953852190780466499102481078740213	4467	UVM_ERROR @ 1918848761 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1918848761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	95278459516732943684069367703384449458417660366799103352124625110669774711563	13866	UVM_ERROR @ 18472407937 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 18472407937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	1171147172746543452385325287146781703335009151666151085118723421080504034506	8739	UVM_ERROR @ 2300693446 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2300693446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	9469710005869198821497084334024800220391851496425017673276899339296324629622	13378	UVM_ERROR @ 5488213829 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5488213829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	14798877763029517088508981621445456463390633600014474862880853852047013910420	13036	UVM_ERROR @ 34025038656 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 34025038656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	29190761239423611214359408010702149547747954914875016033414384660340508058186	4478	UVM_ERROR @ 1541662211 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1541662211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	114111678524616250633237490565574168042452296279988518602646892448526345800864	4132	UVM_ERROR @ 2184091704 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2184091704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	24196041696807608285785729603322322267599611205144573839763585199618802472899	28039	UVM_ERROR @ 28062887919 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 28062887919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---