Simulation Results: csrng

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.46 %
  • code
  • 96.32 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.72 %
  • line
  • 99.61 %
  • branch
  • 96.79 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.75%
V2S
99.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 6.000s 281.244us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 75.980us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 103.845us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 16.000s 406.402us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 7.000s 299.558us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 428.913us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 103.845us 20 20 100.00
csrng_csr_aliasing 7.000s 299.558us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
alerts 500 500 100.00
csrng_alert 43.000s 3431.382us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 136.081us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 484.000s 45187.136us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 484.000s 45187.136us 50 50 100.00
stress_all 46 50 92.00
csrng_stress_all 1372.000s 82265.020us 46 50 92.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 35.605us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 7.000s 179.771us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 12.000s 425.411us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 12.000s 425.411us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 75.980us 5 5 100.00
csrng_csr_rw 3.000s 103.845us 20 20 100.00
csrng_csr_aliasing 7.000s 299.558us 5 5 100.00
csrng_same_csr_outstanding 5.000s 162.454us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 75.980us 5 5 100.00
csrng_csr_rw 3.000s 103.845us 20 20 100.00
csrng_csr_aliasing 7.000s 299.558us 5 5 100.00
csrng_same_csr_outstanding 5.000s 162.454us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
csrng_tl_intg_err 13.000s 596.375us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 4.000s 169.942us 50 50 100.00
csrng_csr_rw 3.000s 103.845us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 43.000s 3431.382us 500 500 100.00
sec_cm_intersig_mubi 46 50 92.00
csrng_stress_all 1372.000s 82265.020us 46 50 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 43.000s 3431.382us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
sec_cm_constants_lc_gated 46 50 92.00
csrng_stress_all 1372.000s 82265.020us 46 50 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 43.000s 3431.382us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 13.000s 596.375us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
csrng_sec_cm 7.000s 119.100us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 19.000s 1089.070us 200 200 100.00
csrng_err 4.000s 136.081us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 376.000s 6556.457us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 4497520511388856386600840855879507832777288924324862536559087924430022140624 175
UVM_ERROR @ 8738675396 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 8738675396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 11770552509864319686241462436984724104374403085218516056991744296486430750918 142
UVM_ERROR @ 12654767 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 12654767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 61882873108131422457279131327387087703210285316442619744157943827005040760588 143
UVM_ERROR @ 3575084637 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 3575084637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 37900453032663140170760434214999745585174819805945554935212506281575678999331 151
UVM_ERROR @ 8255629017 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 8255629017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---