Simulation Results: dma

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.55 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 77.49 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 641.465us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 12.000s 2633.323us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 8.000s 1253.013us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 28.000s 66.785us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 22.000s 20.826us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 33.000s 302.818us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 25.000s 456.794us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 5.000s 44.587us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 22.000s 20.826us 20 20 100.00
dma_csr_aliasing 25.000s 456.794us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 127.000s 8172.171us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 2329.000s 220558.151us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 510.000s 34134.230us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 510.000s 34134.230us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 2329.000s 220558.151us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 507.000s 38460.107us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 510.000s 34134.230us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 25.000s 2438.461us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 412.000s 58201.593us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 18.071us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 28.000s 13.631us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 29.000s 59.491us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 29.000s 59.491us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 28.000s 66.785us 5 5 100.00
dma_csr_rw 22.000s 20.826us 20 20 100.00
dma_csr_aliasing 25.000s 456.794us 5 5 100.00
dma_same_csr_outstanding 8.000s 85.011us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 28.000s 66.785us 5 5 100.00
dma_csr_rw 22.000s 20.826us 20 20 100.00
dma_csr_aliasing 25.000s 456.794us 5 5 100.00
dma_same_csr_outstanding 8.000s 85.011us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 24.000s 272.624us 5 5 100.00
dma_generic_stress 507.000s 38460.107us 5 5 100.00
dma_handshake_stress 510.000s 34134.230us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 1213.352us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 29.000s 52.991us 20 20 100.00
dma_sec_cm 2.000s 22.812us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 180.000s 17356.259us 25 25 100.00
dma_longer_transfer 7.000s 303.019us 5 5 100.00
dma_stress_all_with_rand_reset 17.000s 3762.679us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 97912737108169010680845457261517624925766695188526050049820689535626729368071 125
UVM_ERROR @ 3762678594ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3762678594ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---