Simulation Results: edn

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.52 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
99.94%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.420s 19.292us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.190s 35.213us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.330s 19.059us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 6.050s 351.244us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.800s 42.498us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 139.766us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.330s 19.059us 20 20 100.00
edn_csr_aliasing 1.800s 42.498us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.150s 527.657us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.150s 527.657us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.150s 527.657us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.650s 22.778us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.780s 43.437us 200 200 100.00
errs 100 100 100.00
edn_err 1.790s 26.584us 100 100 100.00
disable 99 100 99.00
edn_disable 1.360s 13.457us 50 50 100.00
edn_disable_auto_req_mode 2.000s 56.506us 49 50 98.00
stress_all 50 50 100.00
edn_stress_all 8.350s 410.979us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.290s 30.313us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 4.990s 248.194us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.880s 527.386us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.880s 527.386us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.190s 35.213us 5 5 100.00
edn_csr_rw 1.330s 19.059us 20 20 100.00
edn_csr_aliasing 1.800s 42.498us 5 5 100.00
edn_same_csr_outstanding 1.740s 106.693us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.190s 35.213us 5 5 100.00
edn_csr_rw 1.330s 19.059us 20 20 100.00
edn_csr_aliasing 1.800s 42.498us 5 5 100.00
edn_same_csr_outstanding 1.740s 106.693us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.630s 247.038us 20 20 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.170s 24.783us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.780s 43.437us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.780s 43.437us 200 200 100.00
edn_sec_cm 23.120s 1906.038us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.780s 43.437us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.630s 247.038us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 92.880s 4541.215us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 107421470313828945425996453210509922054483199510808541886157237716719165211024 87
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---