Simulation Results: edn

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 96.18 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.310s 19.542us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.150s 36.588us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.210s 29.686us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 5.510s 265.745us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.740s 36.620us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.180s 54.820us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.210s 29.686us 20 20 100.00
edn_csr_aliasing 1.740s 36.620us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 80.010s 4582.183us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 80.010s 4582.183us 300 300 100.00
genbits 300 300 100.00
edn_genbits 80.010s 4582.183us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.450s 23.709us 50 50 100.00
alerts 200 200 100.00
edn_alert 2.060s 349.753us 200 200 100.00
errs 100 100 100.00
edn_err 1.520s 26.767us 100 100 100.00
disable 100 100 100.00
edn_disable 1.220s 23.953us 50 50 100.00
edn_disable_auto_req_mode 1.630s 74.375us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 7.550s 516.298us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.210s 17.510us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.960s 91.818us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.860s 293.871us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.860s 293.871us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.150s 36.588us 5 5 100.00
edn_csr_rw 1.210s 29.686us 20 20 100.00
edn_csr_aliasing 1.740s 36.620us 5 5 100.00
edn_same_csr_outstanding 1.830s 148.037us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.150s 36.588us 5 5 100.00
edn_csr_rw 1.210s 29.686us 20 20 100.00
edn_csr_aliasing 1.740s 36.620us 5 5 100.00
edn_same_csr_outstanding 1.830s 148.037us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 6.560s 367.667us 20 20 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.230s 17.775us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.060s 349.753us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.060s 349.753us 200 200 100.00
edn_sec_cm 4.680s 281.799us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.060s 349.753us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 6.560s 367.667us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 94.700s 17275.965us 50 50 100.00

Error Messages

   Test seed line log context