Simulation Results: hmac

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.98 %
  • code
  • 99.32 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.80 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 16.880s 1283.525us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.270s 65.724us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.250s 59.675us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 9.970s 1220.384us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.250s 846.719us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 1521.320s 182162.742us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.250s 59.675us 20 20 100.00
hmac_csr_aliasing 6.250s 846.719us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 92.030s 12518.588us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 86.970s 5816.920us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 270.310s 59707.660us 30 30 100.00
hmac_test_sha384_vectors 576.580s 13771.738us 75 75 100.00
hmac_test_sha512_vectors 638.920s 156748.269us 75 75 100.00
hmac_test_hmac256_vectors 15.210s 341.422us 50 50 100.00
hmac_test_hmac384_vectors 16.760s 795.976us 60 60 100.00
hmac_test_hmac512_vectors 18.250s 1669.763us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 34.520s 2861.441us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1014.050s 24232.656us 10 10 100.00
error 10 10 100.00
hmac_error 163.540s 63533.353us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 138.290s 68195.731us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 16.880s 1283.525us 10 10 100.00
hmac_long_msg 92.030s 12518.588us 10 10 100.00
hmac_back_pressure 86.970s 5816.920us 25 25 100.00
hmac_datapath_stress 1014.050s 24232.656us 10 10 100.00
hmac_burst_wr 34.520s 2861.441us 50 50 100.00
hmac_stress_all 2773.030s 385197.323us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 16.880s 1283.525us 10 10 100.00
hmac_long_msg 92.030s 12518.588us 10 10 100.00
hmac_back_pressure 86.970s 5816.920us 25 25 100.00
hmac_datapath_stress 1014.050s 24232.656us 10 10 100.00
hmac_wipe_secret 138.290s 68195.731us 10 10 100.00
hmac_test_sha256_vectors 270.310s 59707.660us 30 30 100.00
hmac_test_sha384_vectors 576.580s 13771.738us 75 75 100.00
hmac_test_sha512_vectors 638.920s 156748.269us 75 75 100.00
hmac_test_hmac256_vectors 15.210s 341.422us 50 50 100.00
hmac_test_hmac384_vectors 16.760s 795.976us 60 60 100.00
hmac_test_hmac512_vectors 18.250s 1669.763us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 16.880s 1283.525us 10 10 100.00
hmac_long_msg 92.030s 12518.588us 10 10 100.00
hmac_back_pressure 86.970s 5816.920us 25 25 100.00
hmac_datapath_stress 1014.050s 24232.656us 10 10 100.00
hmac_burst_wr 34.520s 2861.441us 50 50 100.00
hmac_error 163.540s 63533.353us 10 10 100.00
hmac_wipe_secret 138.290s 68195.731us 10 10 100.00
hmac_test_sha256_vectors 270.310s 59707.660us 30 30 100.00
hmac_test_sha384_vectors 576.580s 13771.738us 75 75 100.00
hmac_test_sha512_vectors 638.920s 156748.269us 75 75 100.00
hmac_test_hmac256_vectors 15.210s 341.422us 50 50 100.00
hmac_test_hmac384_vectors 16.760s 795.976us 60 60 100.00
hmac_test_hmac512_vectors 18.250s 1669.763us 75 75 100.00
hmac_stress_all 2773.030s 385197.323us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2773.030s 385197.323us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 12.423us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.860s 15.802us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.500s 361.312us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.500s 361.312us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.270s 65.724us 5 5 100.00
hmac_csr_rw 1.250s 59.675us 20 20 100.00
hmac_csr_aliasing 6.250s 846.719us 5 5 100.00
hmac_same_csr_outstanding 2.380s 1725.439us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.270s 65.724us 5 5 100.00
hmac_csr_rw 1.250s 59.675us 20 20 100.00
hmac_csr_aliasing 6.250s 846.719us 5 5 100.00
hmac_same_csr_outstanding 2.380s 1725.439us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.470s 93.698us 5 5 100.00
hmac_tl_intg_err 3.970s 184.502us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 3.970s 184.502us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 16.880s 1283.525us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.720s 441.068us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 690.950s 187596.153us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.520s 308.877us 1 1 100.00

Error Messages

   Test seed line log context