Simulation Results: keymgr

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 99.00 %
  • assert
  • 97.72 %
  • func
  • 91.23 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.18 %
  • toggle
  • 98.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.17%
V2S
99.61%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 21.550s 1087.334us 50 50 100.00
random 50 50 100.00
keymgr_random 22.270s 4409.960us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.510s 58.038us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 24.210s 1279.720us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 10.570s 1989.327us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.510s 50.901us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_csr_aliasing 10.570s 1989.327us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 75.280s 25845.893us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 30.250s 13055.919us 50 50 100.00
keymgr_sideload_kmac 26.910s 2106.970us 50 50 100.00
keymgr_sideload_aes 33.420s 4330.677us 50 50 100.00
keymgr_sideload_otbn 31.030s 1359.025us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 16.950s 4596.685us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 8.810s 249.776us 48 50 96.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 10.380s 813.412us 50 50 100.00
invalid_sw_input 48 50 96.00
keymgr_sw_invalid_input 68.280s 20984.002us 48 50 96.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 35.170s 7947.922us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 22.850s 2053.324us 50 50 100.00
stress_all 47 50 94.00
keymgr_stress_all 439.500s 26464.797us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 1.170s 12.628us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.390s 24.727us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.700s 300.806us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.700s 300.806us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.510s 58.038us 5 5 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_csr_aliasing 10.570s 1989.327us 5 5 100.00
keymgr_same_csr_outstanding 4.230s 1062.596us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.510s 58.038us 5 5 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_csr_aliasing 10.570s 1989.327us 5 5 100.00
keymgr_same_csr_outstanding 4.230s 1062.596us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 9.920s 430.880us 20 20 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.670s 420.277us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.670s 420.277us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.670s 420.277us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.670s 420.277us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.450s 418.811us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.920s 430.880us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.670s 420.277us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 75.280s 25845.893us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_random 22.270s 4409.960us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_random 22.270s 4409.960us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.900s 61.825us 20 20 100.00
keymgr_random 22.270s 4409.960us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 8.810s 249.776us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 35.170s 7947.922us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 35.170s 7947.922us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 22.270s 4409.960us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 31.390s 5292.213us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 19.140s 1124.210us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 8.810s 249.776us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.140s 1124.210us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.140s 1124.210us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.140s 1124.210us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 22.770s 1550.616us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 19.140s 1124.210us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 50 50.00
keymgr_stress_all_with_rand_reset 22.600s 2476.987us 25 50 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 59006345380579703655069217938868301356733176768364542638993752410809684474088 342
UVM_ERROR @ 220195018 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 220195018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43188958990114552904883915296017038761857356158124795509017368441676434765253 104
UVM_ERROR @ 359501486 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 359501486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 44034490541594700571524695758249660786004863998109376859667158365878195169213 284
UVM_ERROR @ 726889632 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 726889632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21675933267716299240604403478720556935483943939714714253342580914591830142882 302
UVM_ERROR @ 950831931 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 950831931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113043872361011030417878769331681511784657712594771230136122111003725897688035 356
UVM_ERROR @ 188800786 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 188800786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 8145103899425990008267964442763782675759742857552872642332635836893581687191 737
UVM_ERROR @ 619753604 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 619753604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63595710528887779047305490475978528277995974203141598461603877033062189353522 539
UVM_ERROR @ 999396902 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 999396902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 7723925077127947401981357747266089752739553934192828489095278944063944295781 268
UVM_ERROR @ 123730090 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123730090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17858978458313180460449078715226116154237034666131192571457140176326134447068 139
UVM_ERROR @ 592411077 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 592411077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11860665558574060401539742665444044752865387559166229783703677170113098721819 299
UVM_ERROR @ 173803674 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 173803674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85505948186152918018889293477168985440777811733077002218330202171909062650581 1579
UVM_ERROR @ 4279239948 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4279239948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 34119853774905063304361962692173470788667478214928240804307750180772523783425 200
UVM_ERROR @ 115374532 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 115374532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 69779902120894759706531307950795261308232209696066517030943876250521866273412 145
UVM_ERROR @ 500394033 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 500394033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 74567556831295180498009039653487536519063769712782907738382250488436825092960 150
UVM_ERROR @ 524853833 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 524853833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 6650143700190517900601447470981185493933732928971303736604216982736678372034 169
UVM_ERROR @ 116646325 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 116646325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56029254188780503033644915514924831768283665985753300498964534545092610904643 175
UVM_ERROR @ 450604720 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 450604720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21660524836424784992874443958995094983028430801148734118234909877683084364009 353
UVM_ERROR @ 557043998 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 557043998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 54595360931374548691794259363753479245128177506422627758277402939228294868301 410
UVM_ERROR @ 122785360 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 122785360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42833787116201776399446669925914210528331103321081076773906860759173527216121 1533
UVM_ERROR @ 2344015741 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2344015741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24631856031874637400400210451475515773349763597859681619900577770352260265995 93
UVM_ERROR @ 1186952246 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1186952246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80379100393049057810937239179195430118979638787705689326578521730562751522914 979
UVM_ERROR @ 834114589 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 834114589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50992622601633745758944569133776617185477833203317964239162458181587454434865 1180
UVM_ERROR @ 1501533332 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1501533332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 115704232572082934353220695809970375668074200265607404632387848310400919744476 171
UVM_ERROR @ 116626688 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 116626688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 33062114107428205191785650997730413577182598517663871394956946979202262869538 852
UVM_ERROR @ 791237965 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 791237965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 53257543947187405725194767912610672047587447306724459568992629022139514679142 1346
UVM_ERROR @ 305161416 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 305161416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 45117274474930951876437028236601901131459720397177962185816115681070815484835 3077
UVM_ERROR @ 844438687 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 844438687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sw_invalid_input 102012577924983058630975749909190800988572655108430592026650197139986192602119 321
UVM_ERROR @ 22664527 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 22664527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sw_invalid_input 14007505946885294562990516153325647961481537698543504313338313705011386027197 110
UVM_ERROR @ 8348601 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 8348601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 39749824793221601181944049046108675423119683423924590800194512640041461808045 1657
UVM_ERROR @ 345122532 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 345122532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Sealing Kmac
keymgr_lc_disable 13894568075683969506508306209093387389100377996965881952478025922693526651392 298
UVM_ERROR @ 221005622 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (13370656734888448382665888268925614264157983029076686710263105052036951303301036424436252896203283632026844297943647941454076758030364596709553706223104578 [0xff4a68a3443fc7ca788b4ae3ed8c1ca4c6861db307ba426a8085a48c1b8e1a96c78f3b4573c26b93a02d788b4c2f060934718d23d8ab3c2dcbb6dbb72ecd7242] vs 13370656734888448382665888268925614264157983029076686710263105052036951303301036424436252896203283632026844297943647941454076758030364596709553706223104578 [0xff4a68a3443fc7ca788b4ae3ed8c1ca4c6861db307ba426a8085a48c1b8e1a96c78f3b4573c26b93a02d788b4c2f060934718d23d8ab3c2dcbb6dbb72ecd7242]) KMAC key at state StOwnerIntKey for Sealing Kmac
UVM_INFO @ 221005622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 49026305589625394491249285935860535810081274437646086085803566240699682346735 661
UVM_ERROR @ 331355192 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
UVM_INFO @ 331355192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_lc_disable 7610830571707892119823331047199943298234664793954116557038995003025683172914 177
UVM_ERROR @ 153868339 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_4
UVM_INFO @ 153868339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---