Simulation Results: keymgr_dpe

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.38 %
  • code
  • 84.26 %
  • assert
  • 97.64 %
  • func
  • 17.25 %
  • line
  • 97.62 %
  • branch
  • 94.61 %
  • cond
  • 90.26 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
99.23%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_dpe_smoke 493.510s 79900.937us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.880s 58.769us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.570s 80.147us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 10.350s 574.289us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 9.380s 1342.613us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.330s 76.832us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.570s 80.147us 20 20 100.00
keymgr_dpe_csr_aliasing 9.380s 1342.613us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.260s 47.485us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.360s 90.465us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 4.730s 754.942us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 4.730s 754.942us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.880s 58.769us 5 5 100.00
keymgr_dpe_csr_rw 1.570s 80.147us 20 20 100.00
keymgr_dpe_csr_aliasing 9.380s 1342.613us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.960s 716.997us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.880s 58.769us 5 5 100.00
keymgr_dpe_csr_rw 1.570s 80.147us 20 20 100.00
keymgr_dpe_csr_aliasing 9.380s 1342.613us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.960s 716.997us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 7.370s 249.674us 20 20 100.00
keymgr_dpe_sec_cm 14.300s 547.289us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.080s 142.028us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.080s 142.028us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.080s 142.028us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.080s 142.028us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 8.120s 237.381us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 14.300s 547.289us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 14.300s 547.289us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: *
keymgr_dpe_csr_mem_rw_with_rand_reset 55071600382699024743108593985449518889312923120350765469363081243321714973443 85
UVM_ERROR @ 27239127 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 27239127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---