Simulation Results: kmac

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 94.36 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.49 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
99.29%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 91.510s 9016.506us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.500s 59.492us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.490s 43.629us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.510s 20550.856us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.830s 140.597us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.120s 349.383us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.490s 43.629us 20 20 100.00
kmac_csr_aliasing 6.830s 140.597us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.150s 37.467us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.810s 22.172us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3819.040s 556606.017us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1421.750s 114179.807us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2144.290s 356518.962us 5 5 100.00
kmac_test_vectors_sha3_256 1639.670s 43888.621us 5 5 100.00
kmac_test_vectors_sha3_384 1071.890s 15415.770us 5 5 100.00
kmac_test_vectors_sha3_512 1334.390s 597846.996us 5 5 100.00
kmac_test_vectors_shake_128 2400.790s 219790.288us 5 5 100.00
kmac_test_vectors_shake_256 1866.450s 58758.640us 5 5 100.00
kmac_test_vectors_kmac 3.970s 138.262us 5 5 100.00
kmac_test_vectors_kmac_xof 4.700s 701.026us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 524.690s 41203.146us 50 50 100.00
app 50 50 100.00
kmac_app 421.140s 49945.420us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 427.560s 76678.655us 10 10 100.00
entropy_refresh 49 50 98.00
kmac_entropy_refresh 412.960s 38218.478us 49 50 98.00
error 50 50 100.00
kmac_error 498.580s 21250.268us 50 50 100.00
key_error 48 50 96.00
kmac_key_error 16.640s 9898.896us 48 50 96.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.580s 548.747us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.320s 2291.029us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.100s 5171.378us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 73.350s 32445.984us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 41.300s 2071.043us 50 50 100.00
stress_all 48 50 96.00
kmac_stress_all 2666.610s 211832.833us 48 50 96.00
intr_test 50 50 100.00
kmac_intr_test 1.030s 79.564us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.410s 55.801us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.980s 221.639us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.980s 221.639us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.500s 59.492us 5 5 100.00
kmac_csr_rw 1.490s 43.629us 20 20 100.00
kmac_csr_aliasing 6.830s 140.597us 5 5 100.00
kmac_same_csr_outstanding 2.630s 92.692us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.500s 59.492us 5 5 100.00
kmac_csr_rw 1.490s 43.629us 20 20 100.00
kmac_csr_aliasing 6.830s 140.597us 5 5 100.00
kmac_same_csr_outstanding 2.630s 92.692us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.870s 143.394us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.870s 143.394us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.870s 143.394us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.870s 143.394us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.110s 439.948us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.890s 1117.355us 20 20 100.00
kmac_sec_cm 115.110s 16398.660us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.890s 1117.355us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 41.300s 2071.043us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 91.510s 9016.506us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 524.690s 41203.146us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.870s 143.394us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 115.110s 16398.660us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 115.110s 16398.660us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 115.110s 16398.660us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 91.510s 9016.506us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 41.300s 2071.043us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 115.110s 16398.660us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 355.220s 53256.467us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 91.510s 9016.506us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 213.480s 3989.330us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 64222099859653586305640297898879068350134337728882057897098376152585808272733 77
UVM_ERROR @ 43617195 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 43617195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 101150035495930458198803369922991186144470375469100262826096373365743415409390 101
UVM_ERROR @ 2635792766 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 2635792766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 48463918400542260093474104924204670052429997568150736975060929671742158903463 76
UVM_ERROR @ 75272558 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 75272558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 95494498677545561018913257742113029521411620217328077664092206501112311051353 368
UVM_ERROR @ 19850832383 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 19850832383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 7629640342042859982736434352161320182082993105062179290344768367892319113852 94
UVM_ERROR @ 2124697657 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 2124697657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 86225630422730895444455766613317612279718524692765565886241793640685814158455 80
UVM_ERROR @ 417930738 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 417930738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 5695667001596280025723472255770113134453877673447477740408911162812621112279 219
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---