Simulation Results: kmac

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 91.97 %
  • assert
  • 97.74 %
  • func
  • 96.40 %
  • line
  • 97.59 %
  • branch
  • 95.97 %
  • cond
  • 94.37 %
  • toggle
  • 100.00 %
  • FSM
  • 71.90 %
Validation stages
V1
100.00%
V2
97.74%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 80.500s 28193.537us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.120s 83.196us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.180s 354.924us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.370s 3431.826us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 4.050s 752.840us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.590s 1337.560us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.180s 354.924us 20 20 100.00
kmac_csr_aliasing 4.050s 752.840us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.720s 35.061us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.300s 137.637us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2806.590s 494664.656us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 904.050s 102012.455us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2136.890s 368504.876us 5 5 100.00
kmac_test_vectors_sha3_256 1179.390s 88220.997us 5 5 100.00
kmac_test_vectors_sha3_384 1270.500s 238316.232us 5 5 100.00
kmac_test_vectors_sha3_512 820.000s 80222.296us 5 5 100.00
kmac_test_vectors_shake_128 2234.560s 105815.689us 5 5 100.00
kmac_test_vectors_shake_256 1269.610s 17816.512us 5 5 100.00
kmac_test_vectors_kmac 2.710s 115.140us 5 5 100.00
kmac_test_vectors_kmac_xof 2.710s 78.323us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 397.750s 19844.283us 50 50 100.00
app 50 50 100.00
kmac_app 300.920s 33106.122us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 286.180s 18202.901us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 320.020s 75945.471us 50 50 100.00
error 49 50 98.00
kmac_error 496.730s 72563.800us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 11.960s 9366.086us 50 50 100.00
sideload_invalid 32 50 64.00
kmac_sideload_invalid 158.070s 10083.105us 32 50 64.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 38.740s 7639.415us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 31.400s 1260.355us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 62.860s 4849.241us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 53.290s 1036.023us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2621.860s 468499.013us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.050s 50.407us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 63.429us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.840s 525.451us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.840s 525.451us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.120s 83.196us 5 5 100.00
kmac_csr_rw 1.180s 354.924us 20 20 100.00
kmac_csr_aliasing 4.050s 752.840us 5 5 100.00
kmac_same_csr_outstanding 2.450s 136.269us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.120s 83.196us 5 5 100.00
kmac_csr_rw 1.180s 354.924us 20 20 100.00
kmac_csr_aliasing 4.050s 752.840us 5 5 100.00
kmac_same_csr_outstanding 2.450s 136.269us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.830s 187.712us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.830s 187.712us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.830s 187.712us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.830s 187.712us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.800s 1394.475us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.650s 988.280us 20 20 100.00
kmac_sec_cm 80.230s 19389.286us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.650s 988.280us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 53.290s 1036.023us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 80.500s 28193.537us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 397.750s 19844.283us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.830s 187.712us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 80.230s 19389.286us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 80.230s 19389.286us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 80.230s 19389.286us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 80.500s 28193.537us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 53.290s 1036.023us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 80.230s 19389.286us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 318.890s 14983.309us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 80.500s 28193.537us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 205.690s 14673.347us 6 10 60.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 82644224673175421782945446392078147372470947125615352984773245018613514931472 85
UVM_FATAL @ 10262105817 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xce1d000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10262105817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 85362518541792560874025513480689044948358585882562150422931720168583880682216 85
UVM_FATAL @ 10386477258 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd1ac7000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10386477258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 109032341864763918763851472183859821501302051506851050416284467001932139884837 355
UVM_ERROR @ 5907388996 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5907388996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 46808279728083191694152731691349031883268710528475544791439690487954221862480 103
UVM_ERROR @ 3590367494 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3590367494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
kmac_stress_all_with_rand_reset 76204421257019991284826016147160643919466612603221128469270603601073917264788 425
UVM_ERROR @ 12239462597 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12239462597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:130) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*]
kmac_stress_all_with_rand_reset 5628015781062684967532225842296780447716953242480307924826834965811102506118 151
UVM_FATAL @ 812899665 ps: (kmac_test_vectors_base_vseq.sv:130) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (32 [0x20] vs 232 [0xe8]) Mismatch between exp_digest[0] and act_digest[0]
UVM_INFO @ 812899665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 102372829405905295229186064066180262189091138047628544772331289225223531969980 75
UVM_FATAL @ 10010175273 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc657b000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10010175273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 114329142970877346366813555864615793951261670833807086840948310951805525364421 75
UVM_FATAL @ 10035039724 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa69f4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10035039724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 33782714359781552930500599448310501935598553384311209921645128446958957314946 75
UVM_FATAL @ 10008688983 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9b83000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008688983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 101103686802735182842785788576552822544483365234235620586141638486814695204477 75
UVM_FATAL @ 10008947920 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x731be000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008947920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 18328873582619809148869987865626344362897836617588506524987230482570578650819 75
UVM_FATAL @ 10041804296 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x44438000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10041804296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 75558133397111042490349677763749509670130702135889298531599236327219038725982 89
UVM_FATAL @ 10093283450 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xde042000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10093283450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 92140780164425658027590952987683743566586398831927285599622873220579550991016 84
UVM_FATAL @ 10066095580 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x127f3000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10066095580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 37363370960023282382941810052238584527285746399138405086927143998758229953175 82
UVM_FATAL @ 10047542746 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x56604000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10047542746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 83882296144160474987223462741171278972736219870894837809690738005343072629599 202
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)
kmac_sideload_invalid 73995173544442102870383172626095281890710991833636045517017523923183104548758 89
UVM_FATAL @ 10083105446 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9ad4d000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10083105446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 38353532456221972077088086684005563631246338203801554482596078848365799325695 89
UVM_FATAL @ 10632288397 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xffc0a000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10632288397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 111871886089980432711628200715062910719995352520520401459600894346422906450397 83
UVM_FATAL @ 10309735143 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa760b000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10309735143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20)
kmac_sideload_invalid 20385031687632150538700734507698586131262532596706882738340026703499840067056 98
UVM_FATAL @ 10331832291 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbc2a4000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10331832291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)
kmac_sideload_invalid 60539998012956288864438892017719539213543172281330732595908476247943101600907 89
UVM_FATAL @ 10100642481 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89bf0000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10100642481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 89747219025414845524162380136036548346761845323381109885397117723314555909521 78
UVM_FATAL @ 10189989960 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa8b3b000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10189989960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 63290511291938073873946824811441226077668635994159936637457696784773159700385 76
UVM_FATAL @ 10037717549 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x48a6c000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10037717549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 74493450557401656002243334581741130141123934653645336686141387024546219895970 77
UVM_FATAL @ 10124569487 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb1e26000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10124569487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---