Simulation Results: mbx

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.59 %
  • code
  • 91.63 %
  • assert
  • 97.01 %
  • func
  • 86.13 %
  • block
  • 96.75 %
  • line
  • 96.71 %
  • branch
  • 92.07 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
99.20%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 46.000s 3856.089us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 21.922us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 8.000s 15.748us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 4.000s 369.854us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 60.444us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 9.000s 210.271us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 8.000s 15.748us 20 20 100.00
mbx_csr_aliasing 2.000s 60.444us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 2 50.00
mbx_stress 52.000s 5557.206us 1 2 50.00
mbx_max_activity 1 2 50.00
mbx_stress_zero_delays 23.000s 1330.361us 1 2 50.00
mbx_imbx_oob 2 2 100.00
mbx_imbx_oob 20.000s 4911.593us 2 2 100.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 20.000s 2243.659us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 2.000s 234.650us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 20.000s 18.119us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 9.000s 101.180us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 9.000s 101.180us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 21.922us 5 5 100.00
mbx_csr_rw 8.000s 15.748us 20 20 100.00
mbx_csr_aliasing 2.000s 60.444us 5 5 100.00
mbx_same_csr_outstanding 8.000s 60.260us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 21.922us 5 5 100.00
mbx_csr_rw 8.000s 15.748us 20 20 100.00
mbx_csr_aliasing 2.000s 60.444us 5 5 100.00
mbx_same_csr_outstanding 8.000s 60.260us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 2.000s 151.657us 5 5 100.00
mbx_tl_intg_err 9.000s 138.711us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 45241138148277108905640222176280130892534026900862399437373082630518787451159 259
UVM_ERROR @ 67218205 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 710309461 [0x2a567655]) RDATA read data mismatched
UVM_INFO @ 67218205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 8044457686080265781614185287199626899736560025508803234009842658469747703873 1019
UVM_ERROR @ 7017404370 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 7017404370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---