Simulation Results: otbn

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 97.22 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • block
  • 99.58 %
  • line
  • 99.68 %
  • branch
  • 95.15 %
  • toggle
  • 94.04 %
  • FSM
  • 100.00 %
Validation stages
V1
99.48%
V2
98.27%
V2S
98.10%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 74.395us 1 1 100.00
single_binary 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 8.000s 21.769us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 14.131us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 12.000s 261.261us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 204.470us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 12.000s 779.460us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 14.131us 20 20 100.00
otbn_csr_aliasing 8.000s 204.470us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 45.000s 1194.467us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 33.000s 1466.509us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 9 10 90.00
otbn_reset 37.000s 106.275us 9 10 90.00
multi_error 1 1 100.00
otbn_multi_err 52.000s 178.312us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 118.000s 302.412us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 133.000s 490.121us 10 10 100.00
lc_escalation 55 60 91.67
otbn_escalate 18.000s 43.449us 55 60 91.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 6.000s 16.196us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 17.000s 887.636us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 33.912us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 8.000s 36.110us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 12.000s 603.116us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 12.000s 603.116us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 8.000s 21.769us 5 5 100.00
otbn_csr_rw 8.000s 14.131us 20 20 100.00
otbn_csr_aliasing 8.000s 204.470us 5 5 100.00
otbn_same_csr_outstanding 8.000s 47.492us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 8.000s 21.769us 5 5 100.00
otbn_csr_rw 8.000s 14.131us 20 20 100.00
otbn_csr_aliasing 8.000s 204.470us 5 5 100.00
otbn_same_csr_outstanding 8.000s 47.492us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 23.000s 78.845us 10 10 100.00
otbn_dmem_err 15.000s 260.080us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 9.000s 211.966us 5 5 100.00
otbn_controller_ispr_rdata_err 101.000s 701.568us 5 5 100.00
otbn_mac_bignum_acc_err 16.000s 92.056us 5 5 100.00
otbn_urnd_err 9.000s 20.017us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 6.000s 59.763us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 295.958us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 7.000s 612.887us 8 10 80.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 30.000s 224.200us 20 20 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
passthru_mem_tl_intg_err 15 20 75.00
otbn_passthru_mem_tl_intg_err 76.000s 472.367us 15 20 75.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 74.395us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 15.000s 260.080us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 23.000s 78.845us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 30.000s 224.200us 20 20 100.00
sec_cm_controller_fsm_global_esc 55 60 91.67
otbn_escalate 18.000s 43.449us 55 60 91.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 23.000s 78.845us 10 10 100.00
otbn_dmem_err 15.000s 260.080us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 16.196us 5 5 100.00
otbn_illegal_mem_acc 6.000s 59.763us 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 23.000s 78.845us 10 10 100.00
otbn_dmem_err 15.000s 260.080us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 16.196us 5 5 100.00
otbn_illegal_mem_acc 6.000s 59.763us 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 55 60 91.67
otbn_escalate 18.000s 43.449us 55 60 91.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 23.000s 78.845us 10 10 100.00
otbn_dmem_err 15.000s 260.080us 15 15 100.00
otbn_zero_state_err_urnd 6.000s 16.196us 5 5 100.00
otbn_illegal_mem_acc 6.000s 59.763us 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 12.000s 40.917us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 8.000s 57.404us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 90.000s 335.374us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 90.000s 335.374us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 14.000s 246.841us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 16.000s 109.168us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 18.000s 267.427us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 18.000s 267.427us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 12.000s 44.244us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 118.000s 302.412us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 8.000s 32.798us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 87.000s 366.368us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4636.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 618.000s 3962.057us 5 10 50.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 23555724020023773817064170695927066189443744159662219623499193739737958298985 88
UVM_FATAL @ 33135691 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 33135691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 29364412275583490300422044970023009449003732198834319384653002857116422524412 108
UVM_FATAL @ 76202266 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 76202266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 36771234632046723666336703456776899336448901858541161197057063136542460074089 88
UVM_FATAL @ 10145300 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 10145300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 57301404778590643205302256844346113986617567677344946409215572225657231170597 83
UVM_FATAL @ 6384792 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 6384792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 42943673179911305502586555498049778908684501361520161100416297532257659489817 93
UVM_FATAL @ 40143321 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 40143321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_escalate 99075515380758412001435741026939705216603288242464351007481947728112768908585 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 146852738 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 146852738 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 146852738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 5604716717544939214600691849808693114933101798577393060497358671644097248112 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 100328472 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 100328472 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 100328472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 57891972742968439670005494123786844803024514986559486573541676135037054432272 587
UVM_ERROR @ 3962057215 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3962057215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 1695321361906331149397697831487313493624664176451391475708531611053967794206 281
UVM_ERROR @ 457060405 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 457060405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 52317878361996597150080528551848446203575568487379856996639491519226521379901 105
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3552230 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3552230 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3552230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 36802000353575439565714640629903768438943658486993113498283851686694676747994 103
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3324386 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3324386 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3324386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_reset 71492092444654076052912307648149856566822847903832497049622191401908752114935 100
UVM_FATAL @ 24939123 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 24939123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 24356798437740999996097835204370122804544019047155204196505167411403151505292 302
UVM_FATAL @ 637003303 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 637003303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 32251512267513154998861163017928333900892905191874470186819571872493231969686 345
UVM_FATAL @ 957860191 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 957860191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 67062182819654010474051779421808874228818530923718022936220292629260060434341 250
UVM_FATAL @ 289390581 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 289390581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 62066139888832592722180537305032868383564425267236664309227300943020194903805 109
UVM_ERROR @ 2755394 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 2755394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 114215757142667865822648441577928762607150040295877269517423571722659726209255 111
UVM_ERROR @ 1670521 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1670521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done.
otbn_escalate 23293742863021680045270116245136446900255663594474247978587480740924592093996 106
UVM_FATAL @ 82697801 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
UVM_INFO @ 82697801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_single 83217386222681020163532892813816905258594361221997932916695345479902372559334 103
UVM_FATAL @ 30887452 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 30887452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---