Simulation Results: rom_ctrl

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.19%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.680s 187.314us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 8.570s 404.166us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.620s 2371.599us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.810s 2105.083us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.140s 345.023us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.460s 175.404us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.620s 2371.599us 20 20 100.00
rom_ctrl_csr_aliasing 6.140s 345.023us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.810s 559.349us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.960s 170.282us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 8.170s 185.860us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 37.560s 4032.570us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.330s 311.039us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.630s 168.279us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.640s 584.461us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.640s 584.461us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.570s 404.166us 5 5 100.00
rom_ctrl_csr_rw 7.620s 2371.599us 20 20 100.00
rom_ctrl_csr_aliasing 6.140s 345.023us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.800s 189.055us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.570s 404.166us 5 5 100.00
rom_ctrl_csr_rw 7.620s 2371.599us 20 20 100.00
rom_ctrl_csr_aliasing 6.140s 345.023us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.800s 189.055us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.210s 620.507us 20 20 100.00
tl_intg_err 22 25 88.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
rom_ctrl_tl_intg_err 64.800s 322.920us 20 20 100.00
prim_fsm_check 2 5 40.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
prim_count_check 2 5 40.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_compare_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
sec_cm_fsm_sparse 2 5 40.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.680s 187.314us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.680s 187.314us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.680s 187.314us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 64.800s 322.920us 20 20 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
rom_ctrl_kmac_err_chk 11.330s 311.039us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 125.190s 3594.763us 19 20 95.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.210s 620.507us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 270.600s 1958.553us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 499.750s 4968.745us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 48023489560417578528852667566243103624664773701162924557333512055260338656580 127
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 27987819ps failed at 27987819ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 27987819ps failed at 27987819ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 107153735027830962405204326777978862773698989499014911846764379299387493744273 368
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 115490521ps failed at 115490521ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 115490521ps failed at 115490521ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 73733725175293752849131141922312940126670301343233481215970709321267808101454 117
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9272238ps failed at 9272238ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9283866ps failed at 9283866ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 12090468044286153368656893518196841726648117063768195378679045991539196389429 87
UVM_ERROR @ 1544606630 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1544606630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---