rom_ctrl Simulation Results

Simulation Results: rom_ctrl

16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	13.200s	298.077us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	17.050s	302.381us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	11.240s	318.277us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	10.720s	299.462us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	10.450s	953.644us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	12.030s	303.728us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	11.240s	318.277us	20	20	100.00
	rom_ctrl_csr_aliasing	10.450s	953.644us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	11.900s	292.907us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	10.600s	537.623us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	9.130s	1965.244us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	47.520s	1102.852us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	20.980s	2106.127us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	11.820s	287.430us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	17.810s	302.932us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	17.810s	302.932us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	17.050s	302.381us	5	5	100.00
	rom_ctrl_csr_rw	11.240s	318.277us	20	20	100.00
	rom_ctrl_csr_aliasing	10.450s	953.644us	5	5	100.00
	rom_ctrl_same_csr_outstanding	13.250s	550.640us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	17.050s	302.381us	5	5	100.00
	rom_ctrl_csr_rw	11.240s	318.277us	20	20	100.00
	rom_ctrl_csr_aliasing	10.450s	953.644us	5	5	100.00
	rom_ctrl_same_csr_outstanding	13.250s	550.640us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	100.440s	6236.747us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_tl_intg_err	145.620s	446.841us	20	20	100.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	13.200s	298.077us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	13.200s	298.077us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	13.200s	298.077us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	145.620s	446.841us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
	rom_ctrl_kmac_err_chk	20.980s	2106.127us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	250.180s	29182.737us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	100.440s	6236.747us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	495.180s	2729.463us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	354.850s	5055.952us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	110791271460303908663449597691870368748260640792006765107914724201239891492144	185	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 19590723ps failed at 19590723ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 19600927ps failed at 19600927ps Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	14774384602679400445188844564518448606221923715269500530739839784615290380588	234	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 56754625ps failed at 56754625ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 64108852ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 64108852ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	40322151301313472978473931310048880633639721782320676675028365403847233620591	177	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 39026742ps failed at 39026742ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 39066742ps failed at 39066742ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	97004893200672243154802040393940811512964451118409418373739458678884895821731	116	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 82556002ps failed at 82556002ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 82556002ps failed at 82556002ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'