rstmgr_cnsty_chk Simulation Results

Simulation Results: rstmgr_cnsty_chk

16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

80.00%

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	rstmgr_cnsty_chk_test	2.770s	11203.190us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	56278987337747595081695693012931972002432455147466838935386008196762841829808	172	UVM_ERROR @ 1766489848 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1784249848 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1802009848 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1819769848 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1837529848 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	99775877874691315107452864874596460527619886029564175227287978167159233714751	172	UVM_ERROR @ 1925193264 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1944553264 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1963913264 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1983273264 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2002633264 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16