| V1 |
|
100.00% |
| V2 |
|
94.38% |
| V2S |
|
100.00% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.730s | 989.933us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.730s | 48.212us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.650s | 15.643us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.910s | 367.434us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.750s | 63.320us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.400s | 124.490us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.650s | 15.643us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.750s | 63.320us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 7.120s | 6473.268us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.960s | 3176.684us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1071.020s | 2121570.913us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1071.020s | 2121570.913us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 5.660s | 6523.110us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.860s | 70.785us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.650s | 14.770us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.400s | 225.577us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.400s | 225.577us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.730s | 48.212us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.650s | 15.643us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.750s | 63.320us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.850s | 72.367us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.730s | 48.212us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.650s | 15.643us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.750s | 63.320us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.850s | 72.367us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.280s | 111.915us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.250s | 197.179us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.250s | 197.179us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 10 | 10.00 | |||
| rv_timer_min | 2.890s | 432.778us | 1 | 10 | 10.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 0.930s | 43.742us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 14 | 20 | 70.00 | |||
| rv_timer_stress_all_with_rand_reset | 58.600s | 28606.589us | 14 | 20 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 94801344961559573129909789434027125286216680186925649058028629920538032358390 | 73 |
UVM_FATAL @ 1060902181 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa6e6dd04) == 0x1
UVM_INFO @ 1060902181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80651410573690375188429138724987790313654196607677258857606961220417953261745 | 72 |
UVM_FATAL @ 302391844 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6a4f7104) == 0x1
UVM_INFO @ 302391844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 10480889637407863551224037249282491400585048279329041329445729621152392516688 | 72 |
UVM_FATAL @ 100005032 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc783704) == 0x1
UVM_INFO @ 100005032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 107754063638822694700806049986473102825676199630725464431636574096241620608108 | 72 |
UVM_FATAL @ 139449688 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4a4d5704) == 0x1
UVM_INFO @ 139449688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 58590588583866171668083472836882029651927626263614997950622746028342437840432 | 73 |
UVM_FATAL @ 128852272 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x63e2b04) == 0x1
UVM_INFO @ 128852272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 79274491013783077705390626563006866540511784916080361306571026231773946329882 | 73 |
UVM_FATAL @ 887335748 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb9da4704) == 0x1
UVM_INFO @ 887335748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 36608549754989741561024338016108304176141613893592561378159377660379138295340 | 72 |
UVM_FATAL @ 72147085 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x77a8b304) == 0x1
UVM_INFO @ 72147085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85076036492844007894123128507314926780883536632308502488593949433872057185458 | 73 |
UVM_FATAL @ 703291169 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x52788704) == 0x1
UVM_INFO @ 703291169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 44280287842094183629305308498857223747535289312252174006734300676737087003122 | 73 |
UVM_FATAL @ 73226733 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc5891704) == 0x1
UVM_INFO @ 73226733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 5298817901222296756123933895715338699204318808453037025099621207937408067117 | 72 |
UVM_FATAL @ 275828130 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf2838104) == 0x1
UVM_INFO @ 275828130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 102897388765863488628248225621332497439090865760240605784146635453048374993234 | 72 |
UVM_FATAL @ 125920484 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc394f304) == 0x1
UVM_INFO @ 125920484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 113019227001696820625913373428161382875834866441367556164399738385257026346515 | 72 |
UVM_FATAL @ 6473267817 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf5edc904) == 0x1
UVM_INFO @ 6473267817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 51882391358347714224968579211639033925921379485507348686856833602624387810720 | 72 |
UVM_FATAL @ 115422510 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd33cb504) == 0x1
UVM_INFO @ 115422510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 9242560727789024470778828611716478439355220569084318271669834676988639569727 | 72 |
UVM_FATAL @ 178160497 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x475ec104) == 0x1
UVM_INFO @ 178160497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 89147005068042450818533397298812091242533921008372522894108491836026271846332 | 72 |
UVM_FATAL @ 94951512 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfe8f304) == 0x1
UVM_INFO @ 94951512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 16928973934236679896202309493296872792881380571912485031305990974882712643501 | 72 |
UVM_FATAL @ 2819045719 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xeebfbf04) == 0x1
UVM_INFO @ 2819045719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 61681282172799294596748100035145035579405304777736919026801102602377250139297 | 73 |
UVM_FATAL @ 432777613 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x18a59904) == 0x1
UVM_INFO @ 432777613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54760908682560125508227148244236839100463807285232568564537975960408317581394 | 72 |
UVM_FATAL @ 334411720 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3a25d504) == 0x1
UVM_INFO @ 334411720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 69300211086907802469072041748763864158054279560476846510067053454655590335215 | 72 |
UVM_FATAL @ 567108353 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x84d87d04) == 0x1
UVM_INFO @ 567108353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 24526079054695974384983168220680301212705801240426707693752543945151279080402 | 72 |
UVM_FATAL @ 545345539 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6827d504) == 0x1
UVM_INFO @ 545345539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 15217350076257637232932575015253627005316981215285124557034033281351265614016 | 74 |
UVM_FATAL @ 216832941 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3a573104) == 0x1
UVM_INFO @ 216832941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 78897489865471391578264909054040486505514016160138894137933571317024371876113 | 72 |
UVM_FATAL @ 79600159 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf9845504) == 0x1
UVM_INFO @ 79600159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 57528029902849427858866734137676533612375812702241243861544527948095504634028 | 73 |
UVM_FATAL @ 85966629 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb8265f04) == 0x1
UVM_INFO @ 85966629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88589175562042652618757220343326521798310680932973655522015842405876509660627 | 73 |
UVM_FATAL @ 795787115 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5feb5904) == 0x1
UVM_INFO @ 795787115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50387970862869919230286025198269047302612286950274828005086790227097256681126 | 72 |
UVM_FATAL @ 246002630 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x26ebd104) == 0x1
UVM_INFO @ 246002630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 97210137737631177811413809603790706223740476526093737620634085974907456492797 | 73 |
UVM_FATAL @ 299340989 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x42d82f04) == 0x1
UVM_INFO @ 299340989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88688101926928678364423099689459954784016483334538261583481154133182067980113 | 73 |
UVM_FATAL @ 151691999 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf23eaf04) == 0x1
UVM_INFO @ 151691999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 1058482761366646918311786905581856552777171389285362765113990975861696697210 | 72 |
UVM_ERROR @ 49365385 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49365385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 86113517134474739605952297547235062050632397869231737295137766252109183036052 | 72 |
UVM_ERROR @ 212897926 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 212897926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64588651978578671809129213201944161921707804907088592856681937397299728884500 | 72 |
UVM_ERROR @ 186195705 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 186195705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 102081583404318186019797250686150953643870833959305282165078353054928623740576 | 72 |
UVM_ERROR @ 89465353 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 89465353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 34007315424708722914787727072901880986766343455348302250816447336720157337826 | 72 |
UVM_ERROR @ 523951892 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 523951892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 31324630714068542767345425360426959820145957025936388540152709486730507111737 | 72 |
UVM_ERROR @ 331950458 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 331950458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 109363137284330937800685986575112779487110907645960257172714493278934492411057 | 72 |
UVM_ERROR @ 43741660 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43741660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 6843518294000073387170774621680425309606769352227179714956278210067052888423 | 72 |
UVM_ERROR @ 50970331 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 50970331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 90618611051393797536799318537223652069142979954325808753228427869419042987140 | 72 |
UVM_ERROR @ 63662998 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 63662998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 20102601157074018478663118741487080716008160823544516702535319089717947531624 | 243 |
UVM_ERROR @ 2297792029 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2297792029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 83650275224128646971008781594751530653855866635132213809480945261922679361269 | 432 |
UVM_ERROR @ 31534979038 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 31534979038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 48856075853974681790302852678313248693041419816416405406486848393375920991310 | 278 |
UVM_FATAL @ 5877618125 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5877618125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 60241362190046959538823459098013057448926056019194314545462347544180955563217 | 308 |
UVM_FATAL @ 9026463249 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 9026463249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 49459926212566103360508456895038669923332406635344851809412628532522160964223 | 305 |
UVM_FATAL @ 3965381862 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3965381862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 74054301566530418811615680953390558263731504621662848441210139939075387879737 | 103 |
UVM_FATAL @ 2635829961 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2635829961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|