Simulation Results: spi_host

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.21%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 90.000s 5587.024us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 43.991us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 43.625us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 637.139us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 45.768us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 29.119us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 43.625us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.768us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 15.494us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 23.730us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 8.000s 26.206us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 38.000s 2715.861us 50 50 100.00
spi_host_error_cmd 9.000s 19.673us 50 50 100.00
spi_host_event 389.000s 551180.571us 50 50 100.00
clock_rate 49 50 98.00
spi_host_speed 18.000s 10049.590us 49 50 98.00
speed 49 50 98.00
spi_host_speed 18.000s 10049.590us 49 50 98.00
chip_select_timing 49 50 98.00
spi_host_speed 18.000s 10049.590us 49 50 98.00
sw_reset 50 50 100.00
spi_host_sw_reset 130.000s 15905.523us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 8.000s 94.409us 50 50 100.00
cpol_cpha 49 50 98.00
spi_host_speed 18.000s 10049.590us 49 50 98.00
full_cycle 49 50 98.00
spi_host_speed 18.000s 10049.590us 49 50 98.00
duplex 50 50 100.00
spi_host_smoke 90.000s 5587.024us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 90.000s 5587.024us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 64.000s 1938.529us 50 50 100.00
spien 49 50 98.00
spi_host_spien 368.000s 11561.418us 49 50 98.00
stall 47 50 94.00
spi_host_status_stall 1126.000s 124780.081us 47 50 94.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 15.000s 2495.061us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 38.000s 2715.861us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 4.000s 18.696us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 6.000s 18.919us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 133.977us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 133.977us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 43.991us 5 5 100.00
spi_host_csr_rw 2.000s 43.625us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.768us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 46.294us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 43.991us 5 5 100.00
spi_host_csr_rw 2.000s 43.625us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.768us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 46.294us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 41.203us 5 5 100.00
spi_host_tl_intg_err 3.000s 83.945us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 83.945us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 206.000s 42511.824us 9 10 90.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
spi_host_status_stall 112950637996480028293266391502517833408185736334226631994443830559177548252808 2891
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 2068122580 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 2068122580 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=2068123000 ps
UVM_INFO @ 2068122580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 93259172118904811897086383972454429379873539996509630410886161810752682989646 2957
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 4026015365 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 4026015365 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=4026015000 ps
UVM_INFO @ 4026015365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 74132401841252787699854502127706528923939142037803375073137624555234366719048 1323
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 22642372776 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 22642372776 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=22642373000 ps
UVM_INFO @ 22642372776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 107593597698093342114473510398170619494582345654635252852713934187473368287704 112
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:220) scoreboard [scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
spi_host_spien 64653181947467398996721974829956891399874396081763934839620507976479717490144 232
UVM_FATAL @ 171641012 ps: (spi_host_scoreboard.sv:220) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
UVM_INFO @ 171641012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_speed 76783797749151219526001399133680639241485113655179089119555748455223602964837 247
UVM_FATAL @ 10049589730 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x7da5e0d4, Comparison=CompareOpEq, exp_data=0x0, call_count=43
UVM_INFO @ 10049589730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---