Simulation Results: sram_ctrl

 
16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.85%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 88.890s 3844.765us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.050s 25.547us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.050s 13.463us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.780s 577.178us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.110s 19.882us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.650s 364.707us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.050s 13.463us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 19.882us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 378.620s 138022.360us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 182.350s 6042.547us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1234.690s 79216.269us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 456.410s 6139.767us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2417.330s 441550.480us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1615.060s 344153.886us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 148.710s 227222.979us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1305.240s 24109.805us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 100.100s 2748.956us 50 50 100.00
sram_ctrl_partial_access_b2b 599.260s 464869.547us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 106.280s 839.188us 50 50 100.00
sram_ctrl_throughput_w_partial_write 103.560s 792.332us 50 50 100.00
sram_ctrl_throughput_w_readback 105.690s 3669.184us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1250.330s 8689.468us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.770s 2790.689us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 6423.740s 241562.505us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.040s 14.092us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.510s 156.662us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.510s 156.662us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 25.547us 5 5 100.00
sram_ctrl_csr_rw 1.050s 13.463us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 19.882us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.180s 28.333us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 25.547us 5 5 100.00
sram_ctrl_csr_rw 1.050s 13.463us 20 20 100.00
sram_ctrl_csr_aliasing 1.110s 19.882us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.180s 28.333us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 67.790s 7215.527us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 3.130s 353.249us 20 20 100.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.130s 353.249us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1250.330s 8689.468us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1250.330s 8689.468us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.050s 13.463us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1305.240s 24109.805us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1305.240s 24109.805us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1305.240s 24109.805us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 148.710s 227222.979us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 43 50 86.00
sram_ctrl_mubi_enc_err 13.830s 13295.404us 43 50 86.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 67.790s 7215.527us 20 20 100.00
sec_cm_mem_readback 39 50 78.00
sram_ctrl_readback_err 9.500s 6007.592us 39 50 78.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 88.890s 3844.765us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 88.890s 3844.765us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1305.240s 24109.805us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 148.710s 227222.979us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 88.890s 3844.765us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.980s 4.951us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 210.830s 7100.763us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 87206749562623843153119616329921573318466118725359493125881177800826499723566 96
UVM_ERROR @ 4951056 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4951056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 108098626040041208699866248401648610259232055468164863781023704694547013560004 96
UVM_ERROR @ 24876963 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 24876963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 53508117229520144600935715484391424335691937003404243505135398121312248638324 96
UVM_ERROR @ 5731896 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5731896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 43534973656009392115616215903593807693583648495461716100943544729829608002759 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1953347 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1953347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 99250275645751324646598699605059129051552057736611851586627267488078828822950 98
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1337874ps failed at 1337874ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 2030605 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2030605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 13569015357548453610216360270620369866472738525509622232794344461968125817716 95
UVM_ERROR @ 3128132496 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x6)
UVM_INFO @ 3128132496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 97665719863332256239331331798320020612190435296524850364888882237181937779935 95
UVM_ERROR @ 660302097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x61)
UVM_INFO @ 660302097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44641570406526581335306769535853601877629819986781932268925388891029090079794 95
UVM_ERROR @ 2273750634 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x41)
UVM_INFO @ 2273750634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30141442585973616917602002279243296449699299909367088426718801193384014234802 95
UVM_ERROR @ 2739979244 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5e) != exp (0x6d)
UVM_INFO @ 2739979244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 42748181575047390493365427760836202983630761494049894793265652930854621975338 95
UVM_ERROR @ 1367201116 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x45) != exp (0xf)
UVM_INFO @ 1367201116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 18154750642154335010129080142832803446855588996194354613659911145767349736244 95
UVM_ERROR @ 677581051 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3b) != exp (0x3)
UVM_INFO @ 677581051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 35957031218986838516144240586688403503884650552522246491473060904542252998420 95
UVM_ERROR @ 1404304056 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1) != exp (0x6e)
UVM_INFO @ 1404304056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 113672084118417952733067131585878628169313649159477111028614818701102351383586 95
UVM_ERROR @ 1344295091 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x32) != exp (0x7d)
UVM_INFO @ 1344295091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 22088053326377621271478007266772481471173397058063875491020020313206717665320 95
UVM_ERROR @ 668658688 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x61) != exp (0x71)
UVM_INFO @ 668658688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 89726287150383606002650959401696132237103009440676883062810290854950640628703 95
UVM_ERROR @ 675276352 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0x55)
UVM_INFO @ 675276352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 113425289224707209352302725972365033829157828176792923477447595564812369848732 95
UVM_ERROR @ 1368764139 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xb) != exp (0x22)
UVM_INFO @ 1368764139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 74609386520255920533397374156485111496950176306981751139017806989130537319421 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2746753574 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2746753574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 8583795941273267034496150307024770242851706551556692915873687426187603067172 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2649167448 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2649167448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 17057433095439408004632213490813838945180748436949252707617974796594481284273 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1373633649 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1373633649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 17101387101862367041110878364471865381806268528988779709257866993953627530681 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1321177985 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1321177985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 69639065917358256935847611748952511434238653064858246424337078643305870266114 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3887447298 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3887447298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 77016083394687196137100424262447660363788000856566117366702517267359739298501 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2736600099 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2736600099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 7592492890595547613544685718489607097607710173095026645039104067068340451364 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 707615878 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 707615878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---