sram_ctrl Simulation Results

Simulation Results: sram_ctrl

16/01/2026 17:05:14 sha: b5ecf83 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.68 %

code
96.12 %

assert
95.79 %

func
98.14 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.57%
V2		100.00%
V2S		93.85%
V3		100.00%

229/230 passed

99.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	105.070s	2929.433us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.040s	19.267us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.050s	23.073us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.380s	242.922us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.070s	53.597us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.980s	44.012us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.050s	23.073us	20	20	100.00
	sram_ctrl_csr_aliasing	1.070s	53.597us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.080s	659.337us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.980s	191.904us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1308.080s	23323.403us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	362.010s	16109.864us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	83.240s	19897.125us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1263.490s	13567.048us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	11.980s	1865.267us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1136.700s	16205.772us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	102.370s	1772.734us	50	50	100.00
	sram_ctrl_partial_access_b2b	567.190s	91167.400us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	95.380s	980.951us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	96.830s	151.555us	50	50	100.00
	sram_ctrl_throughput_w_readback	104.690s	1746.653us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1373.220s	77378.815us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.210s	209.479us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4031.620s	713752.293us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.080s	76.314us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.870s	86.839us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.870s	86.839us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.040s	19.267us	5	5	100.00
	sram_ctrl_csr_rw	1.050s	23.073us	20	20	100.00
	sram_ctrl_csr_aliasing	1.070s	53.597us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.180s	23.703us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.040s	19.267us	5	5	100.00
	sram_ctrl_csr_rw	1.050s	23.073us	20	20	100.00
	sram_ctrl_csr_aliasing	1.070s	53.597us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.180s	23.703us	20	20	100.00

V2S

732/780 passed

93.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.570s	2260.585us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_tl_intg_err	3.560s	628.874us	20	20	100.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.560s	628.874us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1373.220s	77378.815us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1373.220s	77378.815us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.050s	23.073us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1136.700s	16205.772us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1136.700s	16205.772us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1136.700s	16205.772us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	11.980s	1865.267us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				42	50	84.00
	sram_ctrl_mubi_enc_err	1.520s	63.090us	42	50	84.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.570s	2260.585us	20	20	100.00
sec_cm_mem_readback				40	50	80.00
	sram_ctrl_readback_err	1.640s	102.813us	40	50	80.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	105.070s	2929.433us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	105.070s	2929.433us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1136.700s	16205.772us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	11.980s	1865.267us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	105.070s	2929.433us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.230s	5.525us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	695.450s	17370.409us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	47482194360334128918011525501067838978396249185771756926629302411658074260730	95	UVM_ERROR @ 39859738 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 39859738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	33574114554190261232931554350192699351536740749716219898097379162437187663449	100	UVM_ERROR @ 5819918 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 5819918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	99787571934535538639585410541306775772566632020944519176923833451588700785480	100	UVM_ERROR @ 42396285 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 42396285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	28643380143475581970636290788451284192685317420548619964506369944801400636370	97	UVM_ERROR @ 3699231 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3699231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	56780580864274672103207046539329091084567171819884947629428369184615058444319	100	UVM_ERROR @ 5524792 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 5524792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	103925302383975009548773044996351274750424919612560814023990315077701111152490	98	UVM_ERROR @ 24420179 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 24420179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	109411601659595456765801657861496057107640089095092586805284021555807750028034	95	UVM_ERROR @ 52153002 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x10) UVM_INFO @ 52153002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	34999161115440524131248275254600275690281957948367896843395546524138025695024	95	UVM_ERROR @ 44818106 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x46) != exp (0x59) UVM_INFO @ 44818106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	97462827192198743874841375163887171510656225358759183468893003622331740997782	95	UVM_ERROR @ 456761261 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x53) != exp (0x32) UVM_INFO @ 456761261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	78958280059651521114984964540828846409581152417717825865962950874512304965759	95	UVM_ERROR @ 25149015 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7a) != exp (0x75) UVM_INFO @ 25149015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	79511244447967353473686058068598090573798168606189538346232325321377662654021	95	UVM_ERROR @ 82193383 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x19) != exp (0x48) UVM_INFO @ 82193383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	11108816597795736585137143283597712118116695728505834693092485239782979932910	95	UVM_ERROR @ 126428145 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x48) != exp (0x19) UVM_INFO @ 126428145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	36274009414917942765692623976926318107237057427655794707513324677036967362836	95	UVM_ERROR @ 88947350 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x34) != exp (0x73) UVM_INFO @ 88947350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	68705112411016257041404025363559074044832548013077834113115456586275738935357	95	UVM_ERROR @ 65556839 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x71) != exp (0x7d) UVM_INFO @ 65556839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	9229599981079735765076904905203013857313919749018740441886671216653012549543	95	UVM_ERROR @ 171328757 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x1c) UVM_INFO @ 171328757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	56846083676037947624109986133851291004995837136043555297896474336160887525477	95	UVM_ERROR @ 336312545 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x5e) UVM_INFO @ 336312545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	12134646472301543593379783730957994663775010025481179370063310876459531698316	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 166043276 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 166043276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	66295011452360552551614153888353313139885701192585341594608499356093231169045	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 24337745 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 24337745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	79126203607749862904701555559175653371038819704280399712568119460703632636026	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 26671699 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 26671699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	95753575735837675201499796963076028602849903378441161347592322730562481710678	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 27272581 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 27272581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	52831416887590544417144222046048960815392936879025782729144335936931546470004	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 25444619 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 25444619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	1289848736536173189522715458292358428964660278919502021397340300860948629018	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 25787548 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 25787548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	23300787105035186446894193773554696157970558332266809639733224421517159597643	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 82874569 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 82874569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	28705471823613051379118365861701777586922132071773284577173866744373153277075	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 61994878 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 61994878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---