Simulation Results: ac_range_check

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.28 %
  • code
  • 93.54 %
  • assert
  • 97.63 %
  • func
  • 58.67 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 82.34 %
Validation stages
V1
99.17%
V2
97.43%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 59.000s 1420.124us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 88.000s 2447.259us 19 20 95.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 63.443us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 4.000s 180.638us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 62.000s 11684.880us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 5863.853us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 4.000s 21.485us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 4.000s 180.638us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 5863.853us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 150.323us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 39.000s 18260.296us 1 1 100.00
stress_all 42 50 84.00
ac_range_check_stress_all 301.000s 8288.948us 42 50 84.00
alert_test 50 50 100.00
ac_range_check_alert_test 3.000s 22.719us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 3.000s 14.663us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 7.000s 640.503us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 7.000s 640.503us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 63.443us 5 5 100.00
ac_range_check_csr_rw 4.000s 180.638us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 5863.853us 5 5 100.00
ac_range_check_same_csr_outstanding 9.000s 756.615us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 63.443us 5 5 100.00
ac_range_check_csr_rw 4.000s 180.638us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 5863.853us 5 5 100.00
ac_range_check_same_csr_outstanding 9.000s 756.615us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1139.189us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1139.189us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1139.189us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1139.189us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 147.000s 26224.408us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 21.909us 5 5 100.00
ac_range_check_tl_intg_err 16.000s 719.133us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 549.000s 3537.033us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 53.000s 2246.398us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 40684474174675156037915982467785661851329140297514477322090377179558857868487 4217
UVM_ERROR @ 4908834233 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 4908834233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 96383142359119442918444626900730625443572986541884031759863716745600467153108 4508
UVM_ERROR @ 1930769787 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1930769787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 16215758390558588358882196815090256779336385109636667040118893991830260510047 23888
UVM_ERROR @ 22399654460 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 22399654460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 50707310184726579957030442418813488185714738267267797187065121738416003953402 17403
UVM_ERROR @ 58850732261 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 58850732261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 46510441737216055717359960538595035860892702034024789118409167047989373529160 22680
UVM_ERROR @ 20839704113 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 20839704113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 24237956009990728499736072093373610114527667421113120524479735622259550418310 4570
UVM_ERROR @ 3560934821 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3560934821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 38060738921086007454883473006356063005308510435431437314236117044071459866296 17991
UVM_ERROR @ 2554480999 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2554480999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 72576567351449710985555735504169286247926593694895224572984725083133022129457 18339
UVM_ERROR @ 6976044449 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6976044449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
ac_range_check_stress_all 43970231331498749747274714639341493160040805482359679525905490535987222933100 18569
UVM_ERROR @ 100412618604 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
UVM_INFO @ 100412618604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---