Simulation Results: csrng

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.47 %
  • code
  • 96.35 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.76 %
  • line
  • 99.64 %
  • branch
  • 96.88 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.75%
V2S
99.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 4.000s 71.264us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 21.227us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 45.868us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 45.000s 2583.084us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 10.000s 326.762us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 234.445us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 45.868us 20 20 100.00
csrng_csr_aliasing 10.000s 326.762us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
alerts 500 500 100.00
csrng_alert 50.000s 4539.757us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 87.262us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 805.000s 70721.167us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 805.000s 70721.167us 50 50 100.00
stress_all 46 50 92.00
csrng_stress_all 873.000s 58817.564us 46 50 92.00
intr_test 50 50 100.00
csrng_intr_test 5.000s 189.805us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 5.000s 199.341us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 40.000s 210.346us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 40.000s 210.346us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 21.227us 5 5 100.00
csrng_csr_rw 3.000s 45.868us 20 20 100.00
csrng_csr_aliasing 10.000s 326.762us 5 5 100.00
csrng_same_csr_outstanding 8.000s 786.281us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 21.227us 5 5 100.00
csrng_csr_rw 3.000s 45.868us 20 20 100.00
csrng_csr_aliasing 10.000s 326.762us 5 5 100.00
csrng_same_csr_outstanding 8.000s 786.281us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
csrng_tl_intg_err 37.000s 428.797us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 4.000s 96.018us 50 50 100.00
csrng_csr_rw 3.000s 45.868us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 50.000s 4539.757us 500 500 100.00
sec_cm_intersig_mubi 46 50 92.00
csrng_stress_all 873.000s 58817.564us 46 50 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 50.000s 4539.757us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
sec_cm_constants_lc_gated 46 50 92.00
csrng_stress_all 873.000s 58817.564us 46 50 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 50.000s 4539.757us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 37.000s 428.797us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
csrng_sec_cm 5.000s 65.972us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 17.000s 1057.172us 200 200 100.00
csrng_err 4.000s 87.262us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 333.000s 21293.015us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 46366896046009937442522428873374519471537275807645173470653809577830215396813 174
UVM_ERROR @ 5235498016 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 5235498016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 32044566615948181884157629388643543340961506637643427341062909195134904105143 142
UVM_ERROR @ 96879309 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 96879309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 85370939833252705245023040568361911925538004250209266611355115373539776056010 156
UVM_ERROR @ 11977805751 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 11977805751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 38243211513507342579987810974030015592935953316703901776649110556939198746090 153
UVM_ERROR @ 3259897762 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 3259897762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---