Simulation Results: dma

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.71 %
  • code
  • 92.23 %
  • assert
  • 95.97 %
  • func
  • 77.93 %
  • block
  • 97.43 %
  • line
  • 96.94 %
  • branch
  • 95.90 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 328.271us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 1344.986us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 11.000s 394.838us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 48.615us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 33.170us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 16.000s 4152.900us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 1929.210us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 97.378us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 33.170us 20 20 100.00
dma_csr_aliasing 7.000s 1929.210us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 132.000s 10916.735us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1283.000s 386635.770us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 363.000s 85110.925us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 363.000s 85110.925us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1283.000s 386635.770us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 940.000s 68640.724us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 363.000s 85110.925us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 20.000s 5875.292us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 315.000s 36484.340us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 133.587us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 33.045us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 151.901us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 151.901us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 48.615us 5 5 100.00
dma_csr_rw 2.000s 33.170us 20 20 100.00
dma_csr_aliasing 7.000s 1929.210us 5 5 100.00
dma_same_csr_outstanding 4.000s 335.057us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 48.615us 5 5 100.00
dma_csr_rw 2.000s 33.170us 20 20 100.00
dma_csr_aliasing 7.000s 1929.210us 5 5 100.00
dma_same_csr_outstanding 4.000s 335.057us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 35.000s 332.413us 5 5 100.00
dma_generic_stress 940.000s 68640.724us 5 5 100.00
dma_handshake_stress 363.000s 85110.925us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 14.000s 340.087us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 23.682us 5 5 100.00
dma_tl_intg_err 5.000s 709.346us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 185.000s 64073.788us 25 25 100.00
dma_longer_transfer 9.000s 419.896us 5 5 100.00
dma_stress_all_with_rand_reset 31.000s 1404.661us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 81655147864203256272269311443622546091304523419045784206697417277369954933433 156
UVM_ERROR @ 1404660773ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1404660773ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---