Simulation Results: edn

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.32 %
  • code
  • 96.18 %
  • assert
  • 97.14 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.270s 18.525us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.780s 75.242us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.880s 17.970us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.190s 342.653us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 0.970s 23.067us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.320s 26.840us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.880s 17.970us 20 20 100.00
edn_csr_aliasing 0.970s 23.067us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 101.760s 12180.500us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 101.760s 12180.500us 300 300 100.00
genbits 300 300 100.00
edn_genbits 101.760s 12180.500us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.190s 31.500us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.310s 29.269us 200 200 100.00
errs 100 100 100.00
edn_err 1.310s 33.102us 100 100 100.00
disable 100 100 100.00
edn_disable 1.160s 18.453us 50 50 100.00
edn_disable_auto_req_mode 1.460s 43.020us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.810s 393.835us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.770s 19.559us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.290s 93.478us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.690s 135.974us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.690s 135.974us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.780s 75.242us 5 5 100.00
edn_csr_rw 0.880s 17.970us 20 20 100.00
edn_csr_aliasing 0.970s 23.067us 5 5 100.00
edn_same_csr_outstanding 1.120s 44.145us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.780s 75.242us 5 5 100.00
edn_csr_rw 0.880s 17.970us 20 20 100.00
edn_csr_aliasing 0.970s 23.067us 5 5 100.00
edn_same_csr_outstanding 1.120s 44.145us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
edn_tl_intg_err 2.280s 160.722us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.880s 16.287us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.310s 29.269us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.310s 29.269us 200 200 100.00
edn_sec_cm 6.980s 3112.863us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.310s 29.269us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.280s 160.722us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 87.740s 20811.274us 50 50 100.00

Error Messages

   Test seed line log context