Simulation Results: hmac

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.97 %
  • code
  • 99.30 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.130s 899.297us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.230s 72.155us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.280s 37.352us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.840s 1588.402us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.050s 611.538us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 534.580s 237673.832us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.280s 37.352us 20 20 100.00
hmac_csr_aliasing 7.050s 611.538us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 56.290s 10730.586us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 76.610s 1526.136us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 265.710s 32191.852us 30 30 100.00
hmac_test_sha384_vectors 551.350s 31328.612us 75 75 100.00
hmac_test_sha512_vectors 545.830s 14667.870us 75 75 100.00
hmac_test_hmac256_vectors 15.330s 2725.276us 50 50 100.00
hmac_test_hmac384_vectors 17.510s 414.583us 60 60 100.00
hmac_test_hmac512_vectors 19.440s 826.049us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 35.900s 2535.144us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1272.630s 27276.850us 10 10 100.00
error 10 10 100.00
hmac_error 79.250s 1736.520us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 129.580s 61751.904us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.130s 899.297us 10 10 100.00
hmac_long_msg 56.290s 10730.586us 10 10 100.00
hmac_back_pressure 76.610s 1526.136us 25 25 100.00
hmac_datapath_stress 1272.630s 27276.850us 10 10 100.00
hmac_burst_wr 35.900s 2535.144us 50 50 100.00
hmac_stress_all 2516.920s 78543.380us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.130s 899.297us 10 10 100.00
hmac_long_msg 56.290s 10730.586us 10 10 100.00
hmac_back_pressure 76.610s 1526.136us 25 25 100.00
hmac_datapath_stress 1272.630s 27276.850us 10 10 100.00
hmac_wipe_secret 129.580s 61751.904us 10 10 100.00
hmac_test_sha256_vectors 265.710s 32191.852us 30 30 100.00
hmac_test_sha384_vectors 551.350s 31328.612us 75 75 100.00
hmac_test_sha512_vectors 545.830s 14667.870us 75 75 100.00
hmac_test_hmac256_vectors 15.330s 2725.276us 50 50 100.00
hmac_test_hmac384_vectors 17.510s 414.583us 60 60 100.00
hmac_test_hmac512_vectors 19.440s 826.049us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.130s 899.297us 10 10 100.00
hmac_long_msg 56.290s 10730.586us 10 10 100.00
hmac_back_pressure 76.610s 1526.136us 25 25 100.00
hmac_datapath_stress 1272.630s 27276.850us 10 10 100.00
hmac_burst_wr 35.900s 2535.144us 50 50 100.00
hmac_error 79.250s 1736.520us 10 10 100.00
hmac_wipe_secret 129.580s 61751.904us 10 10 100.00
hmac_test_sha256_vectors 265.710s 32191.852us 30 30 100.00
hmac_test_sha384_vectors 551.350s 31328.612us 75 75 100.00
hmac_test_sha512_vectors 545.830s 14667.870us 75 75 100.00
hmac_test_hmac256_vectors 15.330s 2725.276us 50 50 100.00
hmac_test_hmac384_vectors 17.510s 414.583us 60 60 100.00
hmac_test_hmac512_vectors 19.440s 826.049us 75 75 100.00
hmac_stress_all 2516.920s 78543.380us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2516.920s 78543.380us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.930s 15.223us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 14.926us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.310s 259.200us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.310s 259.200us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.230s 72.155us 5 5 100.00
hmac_csr_rw 1.280s 37.352us 20 20 100.00
hmac_csr_aliasing 7.050s 611.538us 5 5 100.00
hmac_same_csr_outstanding 2.670s 141.511us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.230s 72.155us 5 5 100.00
hmac_csr_rw 1.280s 37.352us 20 20 100.00
hmac_csr_aliasing 7.050s 611.538us 5 5 100.00
hmac_same_csr_outstanding 2.670s 141.511us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.240s 71.492us 5 5 100.00
hmac_tl_intg_err 4.060s 778.158us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.060s 778.158us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.130s 899.297us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.610s 163.861us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1170.820s 403869.344us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.770s 32.896us 1 1 100.00

Error Messages

   Test seed line log context