Simulation Results: keymgr

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 98.43 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.09 %
  • branch
  • 98.92 %
  • cond
  • 98.18 %
  • toggle
  • 98.29 %
  • FSM
  • 97.67 %
Validation stages
V1
99.44%
V2
100.00%
V2S
99.61%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 25.770s 4130.056us 50 50 100.00
random 49 50 98.00
keymgr_random 29.130s 1592.421us 49 50 98.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.090s 21.510us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 21.880s 1351.790us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 4.630s 419.906us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 1.760s 114.335us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
keymgr_csr_aliasing 4.630s 419.906us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 86.860s 2436.883us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 38.320s 3260.552us 50 50 100.00
keymgr_sideload_kmac 37.450s 2939.222us 50 50 100.00
keymgr_sideload_aes 34.260s 5810.117us 50 50 100.00
keymgr_sideload_otbn 33.580s 3797.561us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 10.850s 4007.738us 50 50 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 7.250s 373.180us 50 50 100.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 10.470s 678.517us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 48.050s 3977.519us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 37.670s 2381.792us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 11.350s 3629.970us 50 50 100.00
stress_all 50 50 100.00
keymgr_stress_all 380.250s 138604.181us 50 50 100.00
intr_test 50 50 100.00
keymgr_intr_test 1.000s 8.960us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.210s 15.686us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.320s 243.059us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.320s 243.059us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.090s 21.510us 5 5 100.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
keymgr_csr_aliasing 4.630s 419.906us 5 5 100.00
keymgr_same_csr_outstanding 3.300s 399.567us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.090s 21.510us 5 5 100.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
keymgr_csr_aliasing 4.630s 419.906us 5 5 100.00
keymgr_same_csr_outstanding 3.300s 399.567us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
keymgr_tl_intg_err 7.420s 1144.735us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.370s 1056.781us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.370s 1056.781us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.370s 1056.781us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.370s 1056.781us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.750s 602.705us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.420s 1144.735us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.370s 1056.781us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 86.860s 2436.883us 50 50 100.00
sec_cm_reseed_config_regwen 69 70 98.57
keymgr_random 29.130s 1592.421us 49 50 98.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
sec_cm_sw_binding_config_regwen 69 70 98.57
keymgr_random 29.130s 1592.421us 49 50 98.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
sec_cm_max_key_ver_config_regwen 69 70 98.57
keymgr_random 29.130s 1592.421us 49 50 98.00
keymgr_csr_rw 1.310s 117.512us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 7.250s 373.180us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 37.670s 2381.792us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 37.670s 2381.792us 50 50 100.00
sec_cm_hw_key_sw_noaccess 49 50 98.00
keymgr_random 29.130s 1592.421us 49 50 98.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 16.590s 4021.181us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 18.830s 2037.612us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 7.250s 373.180us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 18.830s 2037.612us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 18.830s 2037.612us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 18.830s 2037.612us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 10.600s 1514.932us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 18.830s 2037.612us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 50 50.00
keymgr_stress_all_with_rand_reset 16.470s 634.989us 25 50 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 51592688933815033778297988880473372431314645402317546304172318042747995667402 290
UVM_ERROR @ 150618478 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 150618478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 76592663816768176280620084091738712036780922071706706259554960721054635845895 947
UVM_ERROR @ 391598580 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 391598580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43770644683706076338730437548758999960155385840523997358120540256429328594560 469
UVM_ERROR @ 737666918 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 737666918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 54701207860797623540410679078284836801722345685922749483121107469639272244417 687
UVM_ERROR @ 863384844 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 863384844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 93681582331432386700771911874257204854527792962727815974411490850217995598948 223
UVM_ERROR @ 253828804 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 253828804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 110808254728401216605662360110526838588653887761298452929095843763005794426423 425
UVM_ERROR @ 477665086 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 477665086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 112406421650305859271328871620026705507007806317206656181176981007644771665990 859
UVM_ERROR @ 881982412 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 881982412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 92106958284824767591852456472426430152935448845488873609401408439791731548152 339
UVM_ERROR @ 1031375868 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1031375868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 13031911415297761747518723941693754708362102885360791259156299048944811895458 394
UVM_ERROR @ 970275868 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 970275868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45291459172809618541181622968734497117763107855786475276228685478099832504764 193
UVM_ERROR @ 911308930 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 911308930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 36948688929922415701355614711185657358040306610415870814358610999748763160005 963
UVM_ERROR @ 504622673 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 504622673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1293294187662181678654726614176825807159028421628780919397063167954245186308 94
UVM_ERROR @ 107308694 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107308694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49299044804752442336987071099708393055666209579410051349508649278004589954667 481
UVM_ERROR @ 734268192 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 734268192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79936953014386158170506806842105850121367087798819287704004676788893588492413 882
UVM_ERROR @ 1580333834 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1580333834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95355224079072969832737235720808846969654598949469760753791302837290661262887 125
UVM_ERROR @ 422481955 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 422481955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 41338120778195966095838248559812704302160823588645700196035918912715024866352 178
UVM_ERROR @ 425582033 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 425582033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37367792461588259936528250460756971545529849018373203674439021136841165561580 1240
UVM_ERROR @ 1376626491 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1376626491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107006212517674450707028713878104606890714046635885340625396827635402787536563 174
UVM_ERROR @ 379968500 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 379968500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 32696045981180615114404505674882919248282491254744895052271494072076261615708 215
UVM_ERROR @ 694886165 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 694886165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46713240311005398617336187239188914655397861867421530590859989835207924183895 361
UVM_ERROR @ 183311400 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 183311400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113889621760571555932819928770664159354350945201201722305612288937362704924691 552
UVM_ERROR @ 646927531 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 646927531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83735708909745240063332056953362618125285848415500036784806995508685160557923 226
UVM_ERROR @ 640038053 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 640038053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
keymgr_stress_all_with_rand_reset 22041217566029146376722878806188515134937898901680873324872622211126894038989 582
UVM_ERROR @ 415495458 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (11141408703770496171995778497636277811115822912724857406946203918053071163118431140559295150394451057921367659188899208309864409732499242432205531647022291691160734980885397338613648710389017062278432427470590451963699701603236743672236911423123637793077728720388469108364658245248299712524076935132566503767774024868971543110652464119041907564912 [0x2ea02bc60000000000000000a43c019000000000000000000000000094595993ced7e7b2f60fd7d10ba01fd4e27e8d5b090b88988d5043d9c54c95227712ce5ceef27485f6d8a13e381fe8555e80d595b9b00224bad777a44cd4e36069bb1b8d0e6794a62ca3dae30410849ba2a8a56669802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 42946173421678894431991970180814238486827200284160741465473983095758638072730177038282958624992346297367584806061982105215250483868976945179561093063811150526776235442154240693798567733447862386069176003016797896573357306332103192124385606611346995587732137656705965822482706433061595737033103873243846240294879012312440483892510968339040231039344 [0xb3b9b32340f4740d000000009d04c2b902ec5526000000000000000000000000ced7e7b2f60fd7d10ba01fd4e27e8d5b090b88988d5043d9c54c95227712ce5ceef27485f6d8a13e381fe8555e80d595b9b00224bad777a44cd4e36069bb1b8d0e6794a62ca3dae30410849ba2a8a56669802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0xb9b00224bad777a44cd4e36069bb1b8d0e6794a62ca3dae30410849ba2a8a566, exp: 0xb9b00224bad777a44cd4e36069bb1b8d0e6794a62ca3dae30410849ba2a8a566
HealthMeasurement act: 0xeef27485f6d8a13e381fe8555e80d595, exp: 0xeef27485f6d8a13e381fe8555e80d595
keymgr_stress_all_with_rand_reset 26572616807845791045347781895802152639303314458914507023971829249923255241440 900
UVM_ERROR @ 2164438703 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (6428136149453560337264287604379294221415209801486565585597842041410765162846443075589806268802317382150663750790341415687292533187741606642045151178758871672468664866750930468366539975148594060242517439259720073843606586053820201210014877031840009411600818948496593190081617931259740940800463610261726528490619572308825960529049802298225419690352 [0x1ae6ae7108ec31c1a8af3f025c04f4c100000000ce5d05b300000000e1ec90a2574e188242ad9a6f1b291fe89e6c95837e53df95bed0e807f7d30101bf85ce50a86268a9ce418f3542671b2f2865d85d5311adc309090c7fd63ebaf509fc6a1607091a9bb55ff3eb632d8f264bb55d9269802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 10023538892428855861592469557938907075264512245403950838818822035974868849140090231806529407764129563833658826848497971289058257594299667709773182989087926594607287509427841038759321056200460308237694909855981107948212270547159649583644974276081141543474772071120503218123803985430155020014389300220977539975077095559591878957216394082665719210352 [0x29f28f174ee4900e5864d8480891d3ab5324c11c45b54c8400000000f9eab2e8574e188242ad9a6f1b291fe89e6c95837e53df95bed0e807f7d30101bf85ce50a86268a9ce418f3542671b2f2865d85d5311adc309090c7fd63ebaf509fc6a1607091a9bb55ff3eb632d8f264bb55d9269802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0x5311adc309090c7fd63ebaf509fc6a1607091a9bb55ff3eb632d8f264bb55d92, exp: 0x5311adc309090c7fd63ebaf509fc6a1607091a9bb55ff3eb632d8f264bb55d92
HealthMeasurement act: 0xa86268a9ce418f3542671b2f2865d85d, exp: 0xa86268a9ce418f3542671b2f2865d85d
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
keymgr_stress_all_with_rand_reset 3287068668953247295654727284535663000219746519611972501490330756944762984171 296
UVM_ERROR @ 20854852 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (4 [0x4] vs 6 [0x6])
UVM_INFO @ 20854852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_random 30529660334042819853394784816066335718790600044056781386309081461685415581337 513
UVM_ERROR @ 27239617 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 27239617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---