| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| keymgr_dpe_smoke | 308.280s | 19886.859us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 71.300us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.710s | 92.093us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 8.100s | 295.634us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 5.810s | 619.689us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 2.010s | 39.070us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.710s | 92.093us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.810s | 619.689us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_intr_test | 1.190s | 39.645us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_alert_test | 1.380s | 35.559us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.190s | 118.177us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.190s | 118.177us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 71.300us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.710s | 92.093us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.810s | 619.689us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.170s | 91.107us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 71.300us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.710s | 92.093us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.810s | 619.689us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.170s | 91.107us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| keymgr_dpe_sec_cm | 20.690s | 10196.226us | 5 | 5 | 100.00 | |
| keymgr_dpe_tl_intg_err | 8.920s | 213.024us | 20 | 20 | 100.00 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.170s | 110.290us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.170s | 110.290us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.170s | 110.290us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.170s | 110.290us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 7.190s | 297.710us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 20.690s | 10196.226us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 20.690s | 10196.226us | 5 | 5 | 100.00 | |
| Test | seed | line | log context |
|---|