Simulation Results: kmac

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.53 %
  • code
  • 93.90 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.20 %
  • branch
  • 97.08 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 78.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.80%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 93.030s 9110.803us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.190s 53.417us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.320s 32.533us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.940s 964.645us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.020s 504.392us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.580s 39.662us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.320s 32.533us 20 20 100.00
kmac_csr_aliasing 7.020s 504.392us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.910s 28.416us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.520s 263.053us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3602.110s 182433.323us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1393.690s 86865.077us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2259.320s 98576.043us 5 5 100.00
kmac_test_vectors_sha3_256 44.090s 5670.281us 5 5 100.00
kmac_test_vectors_sha3_384 1604.320s 132699.550us 5 5 100.00
kmac_test_vectors_sha3_512 881.890s 18816.819us 5 5 100.00
kmac_test_vectors_shake_128 2390.630s 306262.006us 5 5 100.00
kmac_test_vectors_shake_256 1884.170s 119473.325us 5 5 100.00
kmac_test_vectors_kmac 3.310s 260.263us 5 5 100.00
kmac_test_vectors_kmac_xof 2.930s 178.292us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 426.780s 7015.238us 50 50 100.00
app 50 50 100.00
kmac_app 345.770s 18214.619us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 444.280s 19231.456us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 366.270s 61942.708us 50 50 100.00
error 50 50 100.00
kmac_error 486.140s 30215.023us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 16.000s 7029.000us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.830s 137.541us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.200s 2323.891us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 33.430s 443.720us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 50.810s 15872.557us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 46.590s 10772.088us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3257.880s 1752906.669us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.090s 17.899us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.310s 92.182us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.290s 246.206us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.290s 246.206us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.190s 53.417us 5 5 100.00
kmac_csr_rw 1.320s 32.533us 20 20 100.00
kmac_csr_aliasing 7.020s 504.392us 5 5 100.00
kmac_same_csr_outstanding 2.570s 93.243us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.190s 53.417us 5 5 100.00
kmac_csr_rw 1.320s 32.533us 20 20 100.00
kmac_csr_aliasing 7.020s 504.392us 5 5 100.00
kmac_same_csr_outstanding 2.570s 93.243us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.200s 74.178us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.200s 74.178us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.200s 74.178us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.200s 74.178us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 4.440s 684.424us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.820s 234.843us 20 20 100.00
kmac_sec_cm 64.930s 8402.549us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.820s 234.843us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 46.590s 10772.088us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 93.030s 9110.803us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 426.780s 7015.238us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.200s 74.178us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 64.930s 8402.549us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 64.930s 8402.549us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 64.930s 8402.549us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 93.030s 9110.803us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 46.590s 10772.088us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 64.930s 8402.549us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 291.520s 14923.752us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 93.030s 9110.803us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 252.920s 6642.319us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 86574775202622415715746552037918010492044844653933877546063380347458605053046 351
UVM_ERROR @ 54481935 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (115605960 [0x6e401c8] vs 3705879975 [0xdce33da7]) Regname: kmac_reg_block.prefix_10 reset value: 0x0
UVM_INFO @ 54481935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 55852383668709802801450194426309847317126226824292028810663727442547079536210 205
UVM_ERROR @ 8508252221 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8508252221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 71824276882746241594433881116184372769406278943793511621509758812647580711556 237
UVM_ERROR @ 8663007376 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8663007376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 11058946373529932508412388608599860860092174945669513165801000730811346033402 213
UVM_ERROR @ 11657098766 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 11657098766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---