Simulation Results: kmac

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 92.17 %
  • assert
  • 97.74 %
  • func
  • 96.26 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.81%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 61.440s 14685.415us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.510s 119.006us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.440s 89.008us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.280s 2920.881us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 12.640s 7631.345us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.780s 73.992us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.440s 89.008us 20 20 100.00
kmac_csr_aliasing 12.640s 7631.345us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.060s 58.926us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.750s 24.364us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2827.310s 129641.736us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 898.840s 205629.164us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 55.310s 2670.738us 5 5 100.00
kmac_test_vectors_sha3_256 1899.430s 856290.604us 5 5 100.00
kmac_test_vectors_sha3_384 1397.490s 47759.961us 5 5 100.00
kmac_test_vectors_sha3_512 945.540s 47974.314us 5 5 100.00
kmac_test_vectors_shake_128 2291.970s 209314.412us 5 5 100.00
kmac_test_vectors_shake_256 259.420s 32166.454us 5 5 100.00
kmac_test_vectors_kmac 2.850s 229.636us 5 5 100.00
kmac_test_vectors_kmac_xof 2.670s 208.874us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 442.480s 89381.945us 50 50 100.00
app 50 50 100.00
kmac_app 276.450s 17341.728us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 284.480s 29714.069us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 378.880s 90536.836us 50 50 100.00
error 50 50 100.00
kmac_error 399.050s 82648.749us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.140s 15093.629us 50 50 100.00
sideload_invalid 40 50 80.00
kmac_sideload_invalid 137.610s 10008.189us 40 50 80.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 42.870s 1608.191us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 43.800s 2291.659us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 56.290s 38676.487us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 44.810s 6318.114us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2137.390s 33175.433us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.140s 22.194us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.280s 171.049us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.440s 51.494us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.440s 51.494us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.510s 119.006us 5 5 100.00
kmac_csr_rw 1.440s 89.008us 20 20 100.00
kmac_csr_aliasing 12.640s 7631.345us 5 5 100.00
kmac_same_csr_outstanding 2.960s 369.189us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.510s 119.006us 5 5 100.00
kmac_csr_rw 1.440s 89.008us 20 20 100.00
kmac_csr_aliasing 12.640s 7631.345us 5 5 100.00
kmac_same_csr_outstanding 2.960s 369.189us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.890s 97.128us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.890s 97.128us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.890s 97.128us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.890s 97.128us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.380s 239.189us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 56.440s 6384.792us 5 5 100.00
kmac_tl_intg_err 4.540s 288.856us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.540s 288.856us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 44.810s 6318.114us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 61.440s 14685.415us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 442.480s 89381.945us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.890s 97.128us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 56.440s 6384.792us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 56.440s 6384.792us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 56.440s 6384.792us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 61.440s 14685.415us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 44.810s 6318.114us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 56.440s 6384.792us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 319.560s 26350.427us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 61.440s 14685.415us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 226.900s 94951.316us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 92994819860560813340863527447210423137920245548179449589902276195262346021159 81
UVM_FATAL @ 10061339033 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf73fb000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10061339033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 63650870329134539635521627217921586948021289147133326438987751094371642731626 82
UVM_FATAL @ 10300433109 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7808c000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10300433109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 15649385128861812590959063782186117046968574451971829648851538545302608434257 208
UVM_ERROR @ 1056039911 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1056039911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 23750388548083569650468788083479603953250938195272301895706777423469563665214 473
UVM_ERROR @ 10483579215 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 10483579215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 23052020949242732500766960446752308869003774190625417304960109269518186912619 87
UVM_FATAL @ 10235797894 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b1cd000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10235797894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 80424684725919350079623608591230124276223645985551639422007205056534353384669 92
UVM_ERROR @ 4178553455 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4178553455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 27496684560043822631223849768421747056154484491311616615380608850753089640080 75
UVM_FATAL @ 10016212719 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x80640000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10016212719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 17704105283526414605319708910936929895452563234260320731460849951656233567340 75
UVM_FATAL @ 10051174454 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x99b0000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10051174454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 76874497755558898310152329174301540551258993762712527909581013326016498086301 75
UVM_FATAL @ 10088740690 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaa1d0000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10088740690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 66107799162818819393038694041921132713742204306357169603522165423892666980210 75
UVM_FATAL @ 10008189211 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9e8ac000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008189211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 70100916741268715818070943251932611871634853596019711262676259646791866726257 79
UVM_FATAL @ 10128576546 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa9795000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10128576546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 85527540934730580095444680533865561685644369342688839953321480201310770624836 95
UVM_FATAL @ 10742948714 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x680b9000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10742948714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 63456959998604594446771423272449882187865431311178648057997752378707533271719 77
UVM_FATAL @ 10292592352 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2cbb3000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10292592352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---