Simulation Results: mbx

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.56 %
  • code
  • 91.55 %
  • assert
  • 97.01 %
  • func
  • 86.13 %
  • block
  • 96.68 %
  • line
  • 96.64 %
  • branch
  • 91.89 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
98.41%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 75.000s 1658.281us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 35.688us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 83.689us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 4.000s 647.365us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 23.997us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 165.945us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 83.689us 20 20 100.00
mbx_csr_aliasing 2.000s 23.997us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 2 0.00
mbx_stress 38.000s 1961.995us 0 2 0.00
mbx_max_activity 0 2 0.00
mbx_stress_zero_delays 28.000s 513.676us 0 2 0.00
mbx_imbx_oob 2 2 100.00
mbx_imbx_oob 72.000s 5438.249us 2 2 100.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 24.000s 566.404us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 3.000s 164.094us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 2.000s 21.095us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 6.000s 679.965us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 6.000s 679.965us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 35.688us 5 5 100.00
mbx_csr_rw 2.000s 83.689us 20 20 100.00
mbx_csr_aliasing 2.000s 23.997us 5 5 100.00
mbx_same_csr_outstanding 3.000s 67.585us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 35.688us 5 5 100.00
mbx_csr_rw 2.000s 83.689us 20 20 100.00
mbx_csr_aliasing 2.000s 23.997us 5 5 100.00
mbx_same_csr_outstanding 3.000s 67.585us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 2.000s 17.213us 5 5 100.00
mbx_tl_intg_err 4.000s 432.966us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 100098263380585660866164659585873604783372832300155615977009291583586800581657 212
UVM_ERROR @ 1961995108 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4019938196 [0xef9b6394] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 1961995108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress 93734909980387679964177100124447818522932903513032330575754758790960862995255 184
UVM_ERROR @ 2010279560 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 3127186418 [0xba6513f2]) RDATA read data mismatched
UVM_INFO @ 2010279560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 7474290081610881777818719330801183161750516720192027575028792565219384282763 111
UVM_ERROR @ 123777362 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 1176931044 [0x46268ae4]) RDATA read data mismatched
UVM_INFO @ 123777362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 94333618266208079720344138657581949080944553778125796098000724897277829566713 166
UVM_ERROR @ 513676256 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 513676256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---