Simulation Results: otbn

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 96.39 %
  • assert
  • 89.72 %
  • func
  • 100.00 %
  • block
  • 99.55 %
  • line
  • 99.65 %
  • branch
  • 94.71 %
  • toggle
  • 93.78 %
  • FSM
  • 97.44 %
Validation stages
V1
99.48%
V2
99.71%
V2S
98.64%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 20.000s 52.202us 1 1 100.00
single_binary 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 6.000s 22.831us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 4.000s 25.347us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 9.000s 96.336us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 6.000s 21.961us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 37.461us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 4.000s 25.347us 20 20 100.00
otbn_csr_aliasing 6.000s 21.961us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 43.000s 1782.622us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 19.000s 365.543us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 149.000s 566.279us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 67.000s 1005.880us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 79.000s 376.874us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 70.000s 1524.323us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 20.000s 76.570us 60 60 100.00
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 9.000s 27.604us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 19.000s 39.265us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 7.000s 25.772us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 7.000s 27.223us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 8.000s 133.879us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 8.000s 133.879us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 6.000s 22.831us 5 5 100.00
otbn_csr_rw 4.000s 25.347us 20 20 100.00
otbn_csr_aliasing 6.000s 21.961us 5 5 100.00
otbn_same_csr_outstanding 6.000s 22.810us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 6.000s 22.831us 5 5 100.00
otbn_csr_rw 4.000s 25.347us 20 20 100.00
otbn_csr_aliasing 6.000s 21.961us 5 5 100.00
otbn_same_csr_outstanding 6.000s 22.810us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 22.000s 78.373us 10 10 100.00
otbn_dmem_err 13.000s 69.540us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 15.000s 52.863us 5 5 100.00
otbn_controller_ispr_rdata_err 14.000s 56.923us 5 5 100.00
otbn_mac_bignum_acc_err 13.000s 58.601us 5 5 100.00
otbn_urnd_err 10.000s 32.141us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 20.713us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 60.218us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 10.000s 53.876us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
otbn_tl_intg_err 35.000s 271.340us 20 20 100.00
passthru_mem_tl_intg_err 17 20 85.00
otbn_passthru_mem_tl_intg_err 28.000s 221.807us 17 20 85.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 20.000s 52.202us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 13.000s 69.540us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 22.000s 78.373us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 35.000s 271.340us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 20.000s 76.570us 60 60 100.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 22.000s 78.373us 10 10 100.00
otbn_dmem_err 13.000s 69.540us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 27.604us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.713us 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 22.000s 78.373us 10 10 100.00
otbn_dmem_err 13.000s 69.540us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 27.604us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.713us 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 20.000s 76.570us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 22.000s 78.373us 10 10 100.00
otbn_dmem_err 13.000s 69.540us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 27.604us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.713us 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 11.000s 41.388us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 33.931us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 27.000s 60.295us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 27.000s 60.295us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 17.000s 57.887us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 14.834s 0.000us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 51.000s 162.820us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 51.000s 162.820us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 20.000s 52.010us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 79.000s 376.874us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 20.000s 42.174us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 635.000s 10044.835us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 238.000s 1096.601us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
otbn_stress_all_with_rand_reset 357.000s 2080.346us 6 10 60.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_rf_bignum_intg_err 46923618710150500820287246012448529264886224390302467051348506274196895538453 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 46923618710150500820287246012448529264886224390302467051348506274196895538453 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3921124629 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_rf_bignum_intg_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_rf_bignum_intg_err.3921124629 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_rf_bignum_intg_err.3921124629 -covoverwrite' seed=46923618710150500820287246012448529264886224390302467051348506274196895538453 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_rf_bignum_intg_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 46923618710150500820287246012448529264886224390302467051348506274196895538453 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest
2026/01/24 05:32:38 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_ctrl_redun 74510736276068781440001346756404559581064152912177543137329431141077397460539 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41388497 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 41388497 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 41388497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 42974221530734684585742966281392826367299257726462177209588961726252970345261 109
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27613045 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 27613045 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 27613045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 33651688512514151841584416169949217354007376225073174259856643800167462681484 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17349921 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 17349921 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 17349921 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17349921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 89775327703387735880879075795565603626289821651141950861249905750806165641223 318
UVM_FATAL @ 320972142 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 320972142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_stress_all_with_rand_reset 73498728797071159999841588617228250903785436538575135901021268274828610926201 411
UVM_FATAL @ 4338948300 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 4338948300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 114420303808088970001358472311277156483983270914212990720219173425514228090957 83
UVM_FATAL @ 12842153 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 12842153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 36501974323718718138444476235964166379128628144511345466297133110161929198259 83
UVM_FATAL @ 1291342 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1291342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 82037759985667433827727193249199593479020483981055620976149327772915421767511 161
UVM_ERROR @ 757424658 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 757424658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 70747936067859948488438830052727686455226446811764120435176907393035897355537 491
UVM_FATAL @ 964012660 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 964012660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete
otbn_single 91639778247197196942664139200905858374629281411236852122745921018826232954993 109
UVM_FATAL @ 10044834898 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
UVM_INFO @ 10044834898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 81381177986562266105547881911393749768142666030503696081161413443559056296967 83
UVM_FATAL @ 4482774 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 4482774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---