rom_ctrl Simulation Results

Simulation Results: rom_ctrl

23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.68 %

code
98.74 %

assert
95.49 %

func
98.81 %

line
99.46 %

branch
99.27 %

cond
95.39 %

toggle
99.59 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		81.13%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	5.990s	572.804us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	8.670s	136.066us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	5.580s	539.037us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	5.950s	123.663us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	7.310s	2098.732us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	7.420s	187.487us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	5.580s	539.037us	20	20	100.00
	rom_ctrl_csr_aliasing	7.310s	2098.732us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	6.180s	2090.351us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	5.370s	173.702us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.280s	182.389us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	26.600s	608.635us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	8.510s	222.085us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	6.690s	168.862us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	9.440s	227.599us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	9.440s	227.599us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.670s	136.066us	5	5	100.00
	rom_ctrl_csr_rw	5.580s	539.037us	20	20	100.00
	rom_ctrl_csr_aliasing	7.310s	2098.732us	5	5	100.00
	rom_ctrl_same_csr_outstanding	8.240s	319.582us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.670s	136.066us	5	5	100.00
	rom_ctrl_csr_rw	5.580s	539.037us	20	20	100.00
	rom_ctrl_csr_aliasing	7.310s	2098.732us	5	5	100.00
	rom_ctrl_same_csr_outstanding	8.240s	319.582us	20	20	100.00

V2S

258/318 passed

81.13 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	24.980s	3295.596us	20	20	100.00
tl_intg_err				20	25	80.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00
	rom_ctrl_tl_intg_err	59.270s	703.915us	20	20	100.00
prim_fsm_check				0	5	0.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00
prim_count_check				0	5	0.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00
sec_cm_checker_ctr_consistency				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_checker_ctrl_flow_consistency				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_checker_fsm_local_esc				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_compare_ctrl_flow_consistency				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_compare_ctr_consistency				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_compare_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00
sec_cm_fsm_sparse				0	5	0.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	5.990s	572.804us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	5.990s	572.804us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	5.990s	572.804us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	59.270s	703.915us	20	20	100.00
sec_cm_bus_local_esc				19	22	86.36
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
	rom_ctrl_kmac_err_chk	8.510s	222.085us	2	2	100.00
sec_cm_mux_mubi				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_mux_consistency				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_ctrl_redun				17	20	85.00
	rom_ctrl_corrupt_sig_fatal_chk	123.250s	4308.588us	17	20	85.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	24.980s	3295.596us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	247.220s	1113.081us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	517.070s	21319.211us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	57238708775237481846520548435127229701416835129154322334908136890234955859408	105	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4941807ps failed at 4941807ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4985285ps failed at 4985285ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	23009188055615484287826571500203801775262468260622563846292894016328007128902	295	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 26588146ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 26588146ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 26588146ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	52333963617020407357086907166506514217207674084025713612021607253547215801090	227	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 15113998ps failed at 15113998ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 15135275ps failed at 15135275ps Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	33757081348894308307720881993969400765154506392285868335291563332326494693412	89	UVM_ERROR @ 864378118 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 864378118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	82382636616158860512502773265274880373279444160600306401125690496880796156202	97	UVM_ERROR @ 1148217559 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1148217559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	41380442384797598586337309945245769933067647438036917833850900343783339424095	89	UVM_ERROR @ 3135819820 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 3135819820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	50768245996842886732397310735142805212024585068389434700234561190939556479618	443	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 120970042ps failed at 120970042ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 121011709ps failed at 121011709ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	76987472057497299858594487915084947239261150223190112466462249406438647801157	108	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10274511ps failed at 10274511ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10274511ps failed at 10274511ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'