rom_ctrl Simulation Results

Simulation Results: rom_ctrl

23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		94.34%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	11.820s	1097.960us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	18.540s	302.324us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	11.070s	533.741us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	10.600s	290.073us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	11.390s	300.740us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	11.600s	296.102us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	11.070s	533.741us	20	20	100.00
	rom_ctrl_csr_aliasing	11.390s	300.740us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	9.170s	297.840us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	9.910s	297.989us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	14.740s	318.520us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	55.300s	11953.898us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	23.100s	571.161us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	11.690s	288.058us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	15.590s	2508.769us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	15.590s	2508.769us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	18.540s	302.324us	5	5	100.00
	rom_ctrl_csr_rw	11.070s	533.741us	20	20	100.00
	rom_ctrl_csr_aliasing	11.390s	300.740us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.510s	1027.713us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	18.540s	302.324us	5	5	100.00
	rom_ctrl_csr_rw	11.070s	533.741us	20	20	100.00
	rom_ctrl_csr_aliasing	11.390s	300.740us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.510s	1027.713us	20	20	100.00

V2S

300/318 passed

94.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	57.800s	25339.473us	20	20	100.00
tl_intg_err				22	25	88.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00
	rom_ctrl_tl_intg_err	127.250s	3858.926us	20	20	100.00
prim_fsm_check				2	5	40.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00
prim_count_check				2	5	40.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_compare_ctr_redun				2	5	40.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00
sec_cm_fsm_sparse				2	5	40.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	11.820s	1097.960us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	11.820s	1097.960us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	11.820s	1097.960us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	127.250s	3858.926us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
	rom_ctrl_kmac_err_chk	23.100s	571.161us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	260.670s	21770.840us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	57.800s	25339.473us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				2	5	40.00
	rom_ctrl_sec_cm	517.460s	769.280us	2	5	40.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	288.090s	3977.566us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	34931650664737230365020086940603144929834638105305137485829682160479170155523	232	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 18196932ps failed at 18196932ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18196932ps failed at 18196932ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	101983531738470844964715094358901703888002506663849814910732392712022002343007	290	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 17325067ps failed at 17325067ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17325067ps failed at 17325067ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	89613119270668838278193229578094776067195553180587039319423818553855361029744	242	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 37330703ps failed at 37330703ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 37343690ps failed at 37343690ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'