Simulation Results: rstmgr

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.56 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 99.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.20%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.950s 72.498us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.800s 93.658us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.130s 67.670us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.730s 52.937us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.520s 98.207us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00
rstmgr_csr_aliasing 1.730s 52.937us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 2.600s 192.259us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.680s 44.659us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.760s 77.288us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 8.540s 701.552us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 8.540s 701.552us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 8.540s 701.552us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 8.540s 701.552us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 48.810s 6155.129us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.550s 57.461us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.400s 83.903us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.400s 83.903us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.800s 93.658us 5 5 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00
rstmgr_csr_aliasing 1.730s 52.937us 5 5 100.00
rstmgr_same_csr_outstanding 1.940s 82.257us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.800s 93.658us 5 5 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00
rstmgr_csr_aliasing 1.730s 52.937us 5 5 100.00
rstmgr_same_csr_outstanding 1.940s 82.257us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 6.820s 616.855us 20 20 100.00
rstmgr_sec_cm 42.820s 6831.106us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 42.820s 6831.106us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 42.820s 6831.106us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 6.820s 616.855us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.760s 61.785us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 48 50 96.00
rstmgr_leaf_rst_cnsty 6.400s 469.135us 48 50 96.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.740s 291.526us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 42.820s 6831.106us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.360s 37.309us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:*
rstmgr_leaf_rst_cnsty 23869619705563698256911744906082702186385964062344433265013867100978719847606 81
UVM_ERROR @ 62281370 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 62281370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 56218321935956577222037474391748310947408469241540980772237487997750537407381 142
UVM_ERROR @ 346752475 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 346752475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---