| V1 |
|
100.00% |
| V2 |
|
94.69% |
| V2S |
|
100.00% |
| V3 |
|
42.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.800s | 990.056us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.780s | 14.771us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.810s | 43.731us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.620s | 353.159us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.980s | 68.134us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.420s | 38.696us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.810s | 43.731us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.980s | 68.134us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 3 | 20 | 15.00 | |||
| rv_timer_random_reset | 8.770s | 29642.794us | 3 | 20 | 15.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.780s | 2067.140us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 665.550s | 1640198.969us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 665.550s | 1640198.969us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.170s | 7494.114us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.850s | 17.888us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.830s | 53.465us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.370s | 140.570us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.370s | 140.570us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.780s | 14.771us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.810s | 43.731us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.980s | 68.134us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.940s | 130.052us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.780s | 14.771us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.810s | 43.731us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.980s | 68.134us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.940s | 130.052us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.480s | 1752.322us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.420s | 914.213us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.420s | 914.213us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.180s | 399.987us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.700s | 481.274us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 63.270s | 13061.822us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 40881365935132656128619719788534777257809549752198081227518572982242986141884 | 73 |
UVM_FATAL @ 62978508 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x22eeaf04) == 0x1
UVM_INFO @ 62978508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 13864478205464934600755413648661733661245427579726455190624144207914239191884 | 72 |
UVM_FATAL @ 191924014 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb48aad04) == 0x1
UVM_INFO @ 191924014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 49312921682529412326155502592683710591689075006811142289729130144630209835445 | 72 |
UVM_FATAL @ 142964361 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xab1b2904) == 0x1
UVM_INFO @ 142964361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98720353350036324504002031412640666625677214086509611137433457668812536981997 | 72 |
UVM_FATAL @ 499094218 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc17e5f04) == 0x1
UVM_INFO @ 499094218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 9476844157418725252526052972290787637365644517830974494218665048512150459901 | 74 |
UVM_FATAL @ 399987159 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdfaed504) == 0x1
UVM_INFO @ 399987159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93443896385764288671623891902767501709307106861290897050056762888188429863611 | 72 |
UVM_FATAL @ 185742160 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5d9be904) == 0x1
UVM_INFO @ 185742160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 80957274435497291574969987853878104057336421457910840959003266092627528534670 | 72 |
UVM_FATAL @ 116694031 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xaac82704) == 0x1
UVM_INFO @ 116694031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 31809220242499005429672933009177289873795903636395667531384510813155537590330 | 72 |
UVM_FATAL @ 428422444 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x56ef7f04) == 0x1
UVM_INFO @ 428422444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 89572381720042092155398825542923215202002272120035360696558601477732278621802 | 73 |
UVM_FATAL @ 269640839 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdff41704) == 0x1
UVM_INFO @ 269640839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 29617263628892557023345187528626168316943151256319917664366627686590961111146 | 72 |
UVM_FATAL @ 65474998 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5a684704) == 0x1
UVM_INFO @ 65474998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 54303641629943964450057187809891863808306385546491408245127656293504658524948 | 72 |
UVM_FATAL @ 67565761 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xef3d4f04) == 0x1
UVM_INFO @ 67565761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65709887709679767007106660718640869584694250053426694253976235239707778888967 | 72 |
UVM_FATAL @ 459769767 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x24b9f04) == 0x1
UVM_INFO @ 459769767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 51996102585113200558528354063952582271655801236535045624257045004117708528296 | 72 |
UVM_FATAL @ 203041300 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x52b0cf04) == 0x1
UVM_INFO @ 203041300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 30568237571242313440882488364815291880968321019957990432177765551728498705166 | 72 |
UVM_FATAL @ 109122937 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x29b19d04) == 0x1
UVM_INFO @ 109122937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 13669986487943514484983705644308657620499485317598753563230115353878594408195 | 75 |
UVM_FATAL @ 147038976 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4a263304) == 0x1
UVM_INFO @ 147038976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 108192451445235151553961999661108226692791432796792415541958628521146360582739 | 72 |
UVM_FATAL @ 86178537 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa9fd4d04) == 0x1
UVM_INFO @ 86178537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 81661758949378960589984779882726779357559253301710649932100770730512499408131 | 73 |
UVM_FATAL @ 64696323 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x14167b04) == 0x1
UVM_INFO @ 64696323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35633335386537949201092593707544252380050199848369930846155737721139557984396 | 74 |
UVM_FATAL @ 100928841 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x823aa904) == 0x1
UVM_INFO @ 100928841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59630499006248330089767168838972570061094320805139408000671472901627970778129 | 72 |
UVM_FATAL @ 29642793918 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x779b0304) == 0x1
UVM_INFO @ 29642793918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82721556437911718569149046503246473204181546672494919609478026792007327868902 | 72 |
UVM_FATAL @ 419763358 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x86a21d04) == 0x1
UVM_INFO @ 419763358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103771000502427414181142225939793995679381499013659395847134243936039368828021 | 72 |
UVM_FATAL @ 320704629 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2bd5ab04) == 0x1
UVM_INFO @ 320704629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 193506631221960490795675799165445678064848301492283336275725626532462748372 | 72 |
UVM_FATAL @ 1211348556 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5257c704) == 0x1
UVM_INFO @ 1211348556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4869200652232017273923933831583794745090150404964493181152729849850557716559 | 73 |
UVM_FATAL @ 467415200 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4a9a5f04) == 0x1
UVM_INFO @ 467415200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 73476810850031215496566466305076908414003697984522177866189234426745646743096 | 72 |
UVM_FATAL @ 753255191 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x35f58f04) == 0x1
UVM_INFO @ 753255191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 19112426795582950246624564009373902605061619383199922387612682886175506097410 | 72 |
UVM_FATAL @ 76547460 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xab41d104) == 0x1
UVM_INFO @ 76547460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 21777522079589265566558449226508774402701847428459029283079692488982897603626 | 72 |
UVM_ERROR @ 42839567 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42839567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 62354437318076796134556923209830972773762783334549870120058486701570995743373 | 73 |
UVM_ERROR @ 172523053 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 172523053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 81534659958673321534095567105532287508809287690105120486969817011740243586454 | 72 |
UVM_ERROR @ 789633413 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 789633413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 30470861612321676741569662346770908492320984428420817760538891723163129472582 | 72 |
UVM_ERROR @ 48537259 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 48537259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 56905670866040995792436724075250026913603942782274242957776672885019942177011 | 72 |
UVM_ERROR @ 168312295 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 168312295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 5080799392945149283145445621867726918451567955350320933044475349878485148334 | 72 |
UVM_ERROR @ 481274324 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 481274324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 83188292633921709748725555257432951940511548997063742838636098275038749928885 | 72 |
UVM_ERROR @ 174990417 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 174990417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 18368542556471723347921498716444533366518087144363387416406356409552857773119 | 73 |
UVM_ERROR @ 543266412 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 543266412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 29493864831175419585754807092013465079990109910123297042696395377792979860130 | 72 |
UVM_ERROR @ 176782957 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 176782957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 9594621368758428062903119589816881041055688180360743688327379198378222411882 | 72 |
UVM_ERROR @ 47042867 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 47042867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 63103358346274427027162272451721179829663380136063095891030975277885800936931 | 210 |
UVM_FATAL @ 7713954804 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 7713954804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 57963951949017220480423321578155930164427618465065536141285825984684568720537 | 158 |
UVM_FATAL @ 5469463984 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5469463984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 99607500089292783195819591531226147184372363384980051257862497536463811939616 | 159 |
UVM_FATAL @ 5468513560 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5468513560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 70303720935851788505539449438598034957066777243413914585451812093429879662195 | 278 |
UVM_FATAL @ 4171269891 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 4171269891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 14636546393497728275510834979359046050596352153582826729911439262182831026301 | 117 |
UVM_ERROR @ 481572449 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 481572449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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